123

Static Timing Jobs

Staff DFT CAD Engineer

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

DFT Domain knowledge technical problem-solving skills VLSI designs Placement Sensors Floor Planning Scan presentations skills Monitors Logic Synthesis communication Memory Testing Routing Logic Testing Static Timing

5 months ago

Full Time position DFT Engineer_Hyderabad/Bangalore_WFO

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

gate-level timing reports EDT compression debug skills Memory BIST implementation RTL-level ATPG constraint issues Scan Verification DFT modes Static Timing

5 months ago

ASIC Digital Design Engr, Sr I

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

Dc hardening Synthesis Dft Fusion Compiler Timing Closure Formality Prime Time UPF Static Timing Analysis

5 months ago

SR Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

power analysis Advanced Node RTL Physical Design low power/multi-voltage physical implementation CAD automation methods floorplanning Timing ASIC implementation DRC closure DRC/LVS Logic Synthesis Placement Parasitic Extraction equivalence checking GDSII Design Methodologies Clock Tree Synthesis static timing analysis routing Python data preparation Perl Tcl

5 months ago

Senior Engineer, Applications Engineering

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

2-3 years

power analysis Sta Extracti on Design Compiler Advanced Node ICC2 Quantus RTL Tempus IRdrop analysis Conformal Physical Design Voltus Front end Synthesis tools Innovus RTL Coding Genus CAD automation methods FusionCompiler Synthesis ASIC implementation Formality DRC/LVS Verification primetime formal checking Back-end P&R tools Star-RCXT redhawk Parasitic Extraction equivalence checking GDSII Design Methodologies static timing analysis Scripting Python Perl Tcl

5 months ago

Senior Applications Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

technical problem-solving Synthesis Repair embedded memories AE deductive Simulation Verbal Communication RTL personal responsibility memory test Dft ASIC Written Communication logic libraries IO libraries self-motivation equivalence checking static timing analysis Soc Verilog Scripting Languages

5 months ago

SoC Design Engg - SD

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

RTL coverage analysis product-level parameters Place And Route EDA Tools power and noise analysis placing Synthesis flow automation power/clock distribution multiple power domain analysis Floor Planning electrical rule checking static and dynamic power integrity Reliability layout verification formal equivalence verification structural design checking physical clock design Gds Timing Closure Dft Clock Tree Synthesis Methodologies static timing analysis routing

5 months ago

Senior Design Engineer - Physical Design

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

Extraction PPA high-speed interfaces floorplanning Asic Physical Design Cadence Full chip Physical Design Signal Integrity clock distribution solutions IR Drop Analysis primetime Design Timing Primetime-SI ASIC fundamentals P&R Synopsys problem-solving skills PERL Static Timing Analysis Scripting Languages Tcl

4 months ago

Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-3 years

Synthesis Design Compiler Logical Equivalence Check Fusion Compiler SERDES serial ata Gate Level simulation RTL PCI Express PrimeTrime Static Timing Analysis

5 months ago

staff engineer

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

Verilog/VHDL RTL level designs gprof timing constrains FPGA prototyping purify C/C++ programming EDA software graph algorithms static timing analysis Digital Logic Design Coverity data structures

5 months ago

FPGA Validation , Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

Data-Analyzers Protocompiler Oscilloscopes AMBA AXI VHDL AWG iSim embedded processors XILINX Vivado UFS floorplanning altera quartus timing constraints definition eMMC Synopsys Synplify APB Modelsim Fpga static timing analysis Vcs Spi DDR Pcie Verilog Computer Architecture I2c System Verilog Python Software Development Bash Operating Systems Perl Ethernet Tcl

5 months ago

Senior Design Engineer- Physical Design

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

Cadence or Synopsys tools Asic Physical Design Full chip Physical Design Cadence Innovus ASIC fundamentals problem-solving skills 5nm node PERL Static Timing Analysis Tcl

4 months ago

SR Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

5 months ago

ASIC Physical Design, Staff Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-9 years

PTECO Timing Constraints Pt DMSA Physical Design static timing analysis automation Python Tcl

5 months ago

DFT engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-20 years

gate-level timing reports EDT compression debug skills Memory BIST implementation RTL-level ATPG constraint issues Scan Verification DFT modes Static Timing

5 months ago

R&D Engineering, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

C/C++ VHDL FPGA design tools graph algorithms timing constrains RTL Verilog static timing analysis Digital Logic Design data structures

5 months ago

Senior STA Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

Sta power analysis static low power checks logic equivalency checks Timing Closure PTPX ECO flows static timing analysis

5 months ago

Member Technical Staff, Signal Integrity

Permanent Job

Bengaluru / Bangalore ,

India

10-18 years

Si Jmp Analog Design lab measurement equipment full wave quasi-static timing budgets TDR Emi electromagnetic Problem-solving Rf Oscilloscopes hfss Hspice system and package level optimization and analysis SIWAVE Printed Circuit Board (PCB layout LPDDR5/6 jitter analysis electrical package design techniques differential and single-ended interface technologies Q3D general I/O design NAND time domain simulation frequency domain simulation PCIe Gen5/6 UFS 5 high-speed single-ended or differential buses DDR5/6 interfaces Doe E.M. field solvers Vector Network Analyzer (VNA transmission line theory Ads Pi Statistical Analysis

5 days ago

CGI Artist

Permanent Job

India

Fresher

Product Visualization final execution Fmcg After Effects style frames Cinema4d Design 3D animations Presentation Skills Adobe Substance Painter 3D Animation photo-manipulation global brand title legibility Layout Premiere Blender Homecare product renderings Compositing Photoshop product visualization integrating CGI models with real-world photography static CGI product photography mobile first Modelling unreal engine Attention To Detail Consumer Goods Maya Typography lighting techniques dynamic posing Octane Storyboarding Timing basic 2D Retouching lighting up-to-date showreel Video Editing social assets Illustrator photorealistic product imagery photorealism compositing in After Effects and Photoshop Vray Redshift animation

13 days ago

Senior Engineer, Signal Integrity

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

4-8 years

Si Jmp Analog Design lab measurement equipment full wave differential quasi-static timing budgets TDR Emi electromagnetic Problem-solving Rf Signal Integrity Oscilloscopes differential buses single-ended interface technologies high-speed single-ended Printed Circuit Board (PCB layout LPDDR5/6 jitter analysis electrical package design techniques general I/O design NAND time domain simulation frequency domain simulation PCIe Gen5/6 UFS 5 DDR5/6 interfaces Doe E.M. field solvers Vector Network Analyzer (VNA transmission line theory system and package level optimization Pi Statistical Analysis

7 days ago

Senior Engineer, Signal Integrity

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

PCIe Gen5/6 E.M. field solvers Oscilloscopes quasi-static lab measurement equipment Vector Network Analyzer (VNA) jitter analysis NAND Problem-solving transmission line theory Si DDR5/6 interfaces Doe timing budgets differential and single-ended interface technologies high-speed single-ended or differential buses TDR Emi system and package level optimization and analysis frequency domain simulation Jmp electromagnetic Rf electrical package design techniques UFS 5 LPDDR5/6 Analog Design general I/O design Printed Circuit Board (PCB) layout time domain simulation full wave Pi Statistical Analysis

9 days ago

Senior Manager - Digital Design development / Verification

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-10 years

LINT cdc high-speed interfaces CPU & IP integration processors RISC-V multiple clock domains power and clock management designs Rtl Design Synthesis BT formal verification static/dynamic clock gating STA Timing Closure low power design methodologies detailed documentation asynchronous interfaces SDIO Design Reviews power gating i2s ARM processors peripheral interfaces dynamic voltage and frequency scaling design signoff flows Mobile DDR Quad/Octa-SPI 15.4 WiFi cross-functional dependencies Pcie Verilog wireless protocols I2c System Verilog Usb Pwm Uart Can Constraints System Architecture Ethernet Ble

15 days ago

Product Specialist SCBU - EDA, Ansys Totem

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Electro Static Discharge Timing Analysis spice simulation tool Electronic Migration IC layout editor Ansys Totem circuit level Eda Tcl Python Perl

21 days ago

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Static Timing Jobs

Staff DFT CAD Engineer

Full Time position DFT Engineer_Hyderabad/Bangalore_WFO

ASIC Digital Design Engr, Sr I

SR Application Engineer

Senior Engineer, Applications Engineering

Senior Applications Engineer

SoC Design Engg - SD

Senior Design Engineer - Physical Design

Application Engineer

staff engineer

FPGA Validation , Staff Engineer

Senior Design Engineer- Physical Design

SR Application Engineer

ASIC Physical Design, Staff Engineer

DFT engineer

R&D Engineering, Staff Engineer

Senior STA Engineer

Member Technical Staff, Signal Integrity

CGI Artist

Senior Engineer, Signal Integrity

Senior Engineer, Signal Integrity

Senior Manager - Digital Design development / Verification

Product Specialist SCBU - EDA, Ansys Totem