144

Rtl Verification Jobs

ASIC Design Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

SOC design Synthesis GLS Team Player Implementation Problem-solving Interpersonal Communication Rtl Design ip design simulation debugging Verification Timing Analysis Dft Physical Design Debugging

3 days ago

ASIC Design Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

SOC design Synthesis GLS Implementation Problem-solving Interpersonal Communication Rtl Design Industry leading design flows ip design simulation debugging Verification Timing Analysis Dft Physical Design Methodologies

3 days ago

DFT DV Lead - SMTS Silicon Design Engineer

Permanent Job

India

0-2 years

Design for Test IEEE1500 Scan Synopsys Tetramax/DFTMAX Perl/Shell scripting Verilog RTL design DFT verification JTAG 1149.x Mentor testkompress memory BIST VCS simulation tool

3 days ago

Sr. DFT DV Engineer

Permanent Job

India

0-2 years

Design for Test IEEE1500 Scan Synopsys Tetramax/DFTMAX Perl/Shell scripting Verilog RTL design DFT verification JTAG 1149.x Mentor testkompress memory BIST VCS simulation tool

2 days ago

CPU/IP SDE/MTS/SMTS Silicon Design Engineer

Permanent Job

India

10-12 years

Asic Design Verification OVM/UVM methodology Digital Design ML/AI OOPs concepts C++ Micro-Architecture ARM Computer Architecture Rtl Design Processor subsystems X86

5 days ago

Silicon Design Engineer 2

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

systemverilog Uvm RTL Mentor Graphics Verification computer organization/architecture Digital Design Cadence Vcs

5 days ago

RTL Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

UVM (Universal Verification Methodology) Clock Domain Crossing (CDC) analysis formal verification techniques systemverilog Rtl Design VHDL Cadence Lint EDA Tools Verification RTL lint tools Synopsys Lint Communication Skills Verilog Python Tcl

4 days ago

Product Engineer - AI/ GenAI

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

VHDL Uvm Verification systemverilog Rtl Design Perl Verilog Python Tcl

4 days ago

AMS Verification Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

Design Verification GDS II AMS Verification Netlist RTL Physical Design Physical Verification Analog Layout

an hour ago

Sr Design verification Engineer- Semiconductor Industry

Permanent Job

Bengaluru / Bangalore ,

India

5-10 years

test bench development Uvm arm architecture UPF Secure boot Rtl Design ASIC constrained random verification processes C/C++ functional coverage low power camera Secure JTAG code coverage Scan Insertion formal verification tools Timing Analysis CPU Security Simulation Tools test pattern generation Regression equivalence checking Verilog Python Perl Tcl

a day ago

Silicon AI/ML Architect, TPU, Google Cloud

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

AI/ML RTL Emulation Go Physical Design ASIC Design Packaging Verification area Power Cost Performance Soc C++ Python Silicon Validation

6 days ago

DESIGN VERIFICATION ENGINEERS (4+ years of Exp Only)

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

Uvm Verification STA-Synthesis Physical Design ASIC flow debugging skill AXI-AMBA protocol variants C/C++ Rtl Design tapeout services Integration System Verilog Makefile Shell Perl

8 days ago

ASIC Digital Design, Principal Engineer

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

high-speed serial interface protocols Debug Silicon debugs/FPGA-based prototyping CDC/RDC/Lint clean analysis DFT insertion customer interactions verification coverage Rtl Design Timing Constraints timing constraints development DFT & Silicon debug cross-team collaborations Verilog RTL design

13 days ago

Senior Manager - Digital Design development / Verification

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-10 years

LINT cdc high-speed interfaces CPU & IP integration processors RISC-V multiple clock domains power and clock management designs Rtl Design Synthesis BT formal verification static/dynamic clock gating STA Timing Closure low power design methodologies detailed documentation asynchronous interfaces SDIO Design Reviews power gating i2s ARM processors peripheral interfaces dynamic voltage and frequency scaling design signoff flows Mobile DDR Quad/Octa-SPI 15.4 WiFi cross-functional dependencies Pcie Verilog wireless protocols I2c System Verilog Usb Pwm Uart Can Constraints System Architecture Ethernet Ble

12 days ago

Sr Staff/Staff ASIC Digital Design Engr (Formal Verification Specialist)

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

Rtl Design HDLs formal verification Static Timing Flows Temporal Logic Assertions digital logic Synthesis Flow Verilog System Verilog Shell Scripting Python Perl

11 days ago

Sr Staff/Staff ASIC Digital Design Engr (Formal Verification Specialist)

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

Rtl Design HDLs formal verification Static Timing Flows Temporal Logic Assertions digital logic Synthesis Flow Verilog System Verilog Shell Scripting Python Perl

11 days ago

ASIC Verification Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-4 years

1510000 - 2559000 INR

Asic verification RTL Debussy Uvm Shell Perl Vcs Gdb System Verilog Python

11 days ago

Design Verification Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

4-6 years

Asic verification Functional Verification Simulation Uvm systemverilog Rtl Design Scripting Python

13 days ago

SMTS Silicon Design Engineer

Permanent Job

India

0-2 years

DFT verification VCS simulation tool IEEE1500 Synopsys Tetramax/DFTMAX JTAG 1149.x Verilog RTL design Scan memory BIST Mentor testkompress Perl/Shell scripting Design for Test

9 days ago

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

Physical Design equivalence checks CTS strategies performance optimization primetime Scan boundary scan power integrity Jtag protocols timing ECO implementation RTL TestMax ATPG STA setup automation scripts static timing verification System Verilog Logic Equivalency checking BIST architectures die size optimization Timing Closure Dft memory BIST Tessent tool sets TetraMax Tcl Python PERL Shell

12 days ago

PMTS Silicon Design Engineer ( DFX Architect )

Permanent Job

India

0-2 years

Design for Test Synopsys Tetramax Perl/Shell scripting Verilog RTL design DFT verification Mentor testkompress VCS simulation tool

14 days ago

SMTS Silicon Design Engineer ( DFx verification Lead )

Permanent Job

India

0-2 years

Design for Test IEEE1500 Scan Synopsys Tetramax/DFTMAX Perl/Shell scripting Verilog RTL design DFT verification JTAG 1149.x Mentor testkompress memory BIST VCS simulation tool

13 days ago

STA/Synthesis Engineer

Permanent Job

Chennai ,

India

2-4 years

Rtl Design Synthesis UPFs Low Power cdc micro-architecture VHDL Linting Implementation formal verification Timing Analysis ASICs Debugging Scripting Verilog Tcl System Verilog Pearl Python

10 days ago

Senior Manager, ASIC Development Engineering - Physical Desing

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design physical design tools design rule checks full-chip Redistribution Layer foundry partners process variations Timing Analysis Placement Cadence Electrical manufacturability Problem-solving Signal Integrity Verification tape-out criteria Synopsys Floor Planning Dfm RTL bump Teamwork Reliability timing optimization mechanical layout versus schematic electrical rule checks advanced process nodes packaging interface Packaging communication RDL Dft power analysis Methodologies routing

12 days ago

Design Engineer (RTL design & FPGA)

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

2-4 years

timing closure techniques Design Verification Analytical Skills Problem-solving Rtl Design VHDL advancements ASIC Design FPGA architectures collaborative team environment FPGA implementation tools communication Documentation FPGA-based systems systemverilog industry trends Verilog Functional Testing Scripting Languages Python FPGA Design Perl Logic Design Tcl

11 days ago

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Rtl Verification Jobs

ASIC Design Engineer

ASIC Design Engineer

DFT DV Lead - SMTS Silicon Design Engineer

Sr. DFT DV Engineer

CPU/IP SDE/MTS/SMTS Silicon Design Engineer

Silicon Design Engineer 2

RTL Design Engineer

Product Engineer - AI/ GenAI

AMS Verification Engineer

Sr Design verification Engineer- Semiconductor Industry

Silicon AI/ML Architect, TPU, Google Cloud

DESIGN VERIFICATION ENGINEERS (4+ years of Exp Only)

ASIC Digital Design, Principal Engineer

Senior Manager - Digital Design development / Verification

Sr Staff/Staff ASIC Digital Design Engr (Formal Verification Specialist)

Sr Staff/Staff ASIC Digital Design Engr (Formal Verification Specialist)

ASIC Verification Engineer

Design Verification Engineer

SMTS Silicon Design Engineer

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

PMTS Silicon Design Engineer ( DFX Architect )

SMTS Silicon Design Engineer ( DFx verification Lead )

STA/Synthesis Engineer

Senior Manager, ASIC Development Engineering - Physical Desing

Design Engineer (RTL design & FPGA)