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I2s Jobs in Hyderabad Secunderabad Telangana
Senior Manager - Digital Design development / Verification
Silicon Labs
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
5-10 years
LINT
cdc
high-speed interfaces
CPU & IP integration
processors
RISC-V
multiple clock domains
power and clock management designs
Rtl Design
Synthesis
BT
formal verification
static/dynamic clock gating
STA Timing Closure
low power design methodologies
detailed documentation
asynchronous interfaces
SDIO
Design Reviews
power gating
i2s
ARM processors
peripheral interfaces
dynamic voltage and frequency scaling
design signoff flows
Mobile DDR
Quad/Octa-SPI
15.4
WiFi
cross-functional dependencies
Pcie
Verilog
wireless protocols
I2c
System Verilog
Usb
Pwm
Uart
Can
Constraints
System Architecture
Ethernet
Ble
11 days ago
Senior SW Embedded Audio Engineer
Qualcomm
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
0-2 years
Noise suppression
i2s
Audio Effects
AMR
FLAC
AAC
EVS
Echo Cancellation
audio/speech compression standards
audio/speech pre/post processing
real time operating systems
DSP platforms
SPDIF
audio interfaces
HDMI
multi-threaded programming
MP3
C
Java
C++
Jtag
Python
Trace32
19 days ago
Senior Engineer - DSP
Qualcomm
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
2-3 years
Audio Interfaces like I2S
optimization for MIPS
audio use cases
audio/speech pre/post processing
Memory
real time operating systems
audio/speech compression standards
multi-threaded programming
tools and techniques used on DSP platforms
SPDIF
voice use cases
HDMI
Java
C
C++
Python
a month ago
Staff Engineer - SoC / chip Design
Silicon Labs
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
10-12 years
resets
RISC-V
formal verification
chip architectures
mixed signal IP
Wireless Systems
i2s
MBIST
ATPG
dynamic voltage and frequency scaling
LINT
cdc
high-speed interfaces
AI accelerators
Synthesis
Dft
static/dynamic clock gating
hardware accelerators
multi-level caches
STA Timing Closure
power management
SDIO
low power design methodology
multiple clocks
interconnects
power gating
multi-threaded processor subsystems
Memory Architecture
Scan
design signoff flows
Mobile DDR
Quad/Octa-SPI
Soc
Pcie
I2c
System Verilog
Usb
Uart
multi-core
Verilog
Python
Pwm
Peripherals
Can
Constraints
Shell
Perl
Ethernet
Arm
Tcl
5 months ago
1
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