Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 6 years of experience in micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, Physical Layer Device.
- Experience with Verilog or System verilog language.
Preferred qualifications:
- Experience in High performance design, Multi power domains with Complex clocking. Proven record of multiple SoCs with silicon success.
- Experience in micro architecture design and knowledge of system design to develop highly optimized IPs with excellent PPA.
- Experience in chip design flow and understanding of cross domain involving Domain Validation / Design for testing / Physical Design.
- Experience in various quality checks performed at the front end including Lint, CDC/RDC, Synthesis, Line Echo Cancellation, etc.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead a team of RTL engineers with IP development plan tasks, hold code and design reviews, code development of complex features in the IP.
- Collaborate with the architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for the IP.
- Collaborate with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
