- As a member of our focused group of HW engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both SDK and backend teams for performance tuning, area, and power optimizations of multi million gate design.
EDUCATION AND EXPERIENCE
- BE/BTech/ME/MTech in Computer Science or Electronics or Electrical
REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES
- Capability to understand a given block specification and come up with Micro Architecture
- Capability to derive an architecture and micro architecture based on a given algorithm
- Experience in processor design RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design.
- Knowledge in digital logic for HW safety/protection ECC, Parity, WDT etc.
- Experience of multi-million gate ASIC design and verification methodologies
- Good understanding of Computer Architecture, ISA, Caches and Memory Hierarchy.
- Experience in performance and power analysis of processor based systems.
- Experience in AMBA AXI, AHB, and APB protocols
- Knowledge of digital design methodologies and tool flow
- Excellent logic design, debugging and problem-solving skills.
- Experience in logic design with Verilog and/or System Verilog and validation/verification
- Experience in lint checks, area optimization, power optimization, GLS, synthesis and timing analysis
- Experience in Multi-clock domain, Interconnects
- Knowledge on Memory subsystem
- Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus.
- Experience with DSP, Datapath design and floating-point math a plus
- Understanding of GPU/AI/ML Processor architecture
