Contribute to the RTL delivery for a multitude of projects
Work closely with system architects to define high level specifications that are implementable and robust, and Interface with verification/validation teams to ensure design quality and robustness.
Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
Promote continuous improvement to design techniques to ensure Zero Defect chips
Collaborate with SME s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence
Qualifications
At least 7+ years of experience in related domains and have working knowledge
Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design.
Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
Experience and knowledge of Verilog, System Verilog, C/C++, Shell.
Good knowledge in scripting like Perl, TCL or Python is a plus.
Proficiency in Metric Driven Verification concepts, functional and code coverage.
Expertise in directed and constrained random methodologies.
Good knowledge of formal verification methodologies and assertions.
Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
Excellent written and verbal communication skills.
Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc) is required, as well as highly efficient FE methodologies.
Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.
