Skills:
Physical Design, PNR, STA, floorplanning, Full chip, Synopsys Tools,
Roles & Responsibilities
- Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Clock Tree planning & analysis, Routing ,Timing Budgeting. Signoff STA closure with SI analysis , Derate etc. ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
- Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold
Job Description
- Good exposure in handling block/SOC level RTL-gds2.
- Capable in handling block-level timing closure.
- Excellent knowledge on all low power & signoff checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.
- Good scripting skills (TCL/SHELL/PERL).
- Experience on low power implementation techniques is preferred.
- Prior experience in lower tech nodes like 10nm, 7nm, 5nm is preferred.
- Synopsys/Cadence tool experience is preferred.
- Should be comfortable with Signoff methodologies and guidelines.
- Expertise in Floor Planning, Power Planning, CTS.
- Handling Client requirements and day to day activities
Requirements
Required Qualification:
- Bachelors degree in Electronics & Communication/Electrical & Electronics. Masters degree in VLSI is preferred.
- Experience 8+ years of relevant experience
- Proven ability to identify, assess and solve problems
- Analytical with good interpersonal skills
- Good Communication
- Excellent team player
- High Integrity
- Mentoring Team Members
- Prior experience of leading a team of 5-8 Engineers.
