Floorplanning Jobs

Technical Staff Engineer - Physical Design

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

Vlsi low-power design methodologies place-and-route system-level floorplanning EM Reliability analytical Calibre Interpersonal Abilities Innovus redhawk power network planning Timing Closure Leadership Skills power integrity IR analysis Clock Tree Synthesis Communication Skills Debugging Tcl Logic Design Perl scripting

2 days ago

Physical Design - Engineer

Permanent Job

Chennai ,

India

1-3 years

floorplanning LEC Pv analytical Sta Problem Solving FV Clock Tree Synthesis PDN power analysis Placement low power verification PNR Unix Clp Linux Tcl Perl

5 days ago

Principal Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design Implementation fast-paced EDA Tools problem-solving skills Placement floorplanning physical design flows power optimization techniques advanced process nodes communication Signal Integrity design teams dynamic environment Multiple Projects Timing Closure Leadership Skills Clock Tree Synthesis Static Timing Analysis routing

11 days ago

Technologist, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design Process Nodes EDA Tools power optimization Placement floorplanning Signal Integrity Routing Static Timing Analysis

11 days ago

Senior Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

foundary requirements IO ring higherarchial design implementation floorplanning PG creation Packaging HMs Analog components PV clean-up Innovus tiles push down Physical Verification Physical Design latch-up Esd RDL placement strategies Partitions Scripting

11 days ago

Principal Engineer - Physical Design

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

place-and-route power network planning Vlsi EM/IR analysis analytical Reliability system-level floorplanning low-power design methodologies Innovus Calibre Leadership Skills redhawk Timing Closure Interpersonal Abilities Communication Skills Clock Tree Synthesis power integrity Perl scripting Debugging Logic Design Tcl

8 days ago

Silicon CAD EDA Methodology Lead, TPU Google Cloud

Permanent Job

Bengaluru / Bangalore ,

India

8-14 years

Chip Design hardware electronic design automation tools AI/ML Physical Design sign-off floorplanning Python C++ Software Automation

29 days ago

Senior Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-15 years

Sta CTS Chip finishing floorplanning Power Integrity Analysis PnR Suite Advanced Physical Verification Techniques Physical Verification Tcl/Tk/Perl Low Power Placement Netlist2GDSII Implementation SOC integration EM/IR-Drop analysis Power Grid Design high speed design Routing Static Timing Analysis

a month ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-5 years

cdc analytical clock domain crossing Physical Design Problem-solving EDA Tools Optimization Si semiconductor engineering ics Documentation floorplanning Vlsi Design Physical Verification project objectives Signal Integrity best practices Timing Closure Placement power integrity Eda routing Python Perl Pi Tcl

a month ago

Principal Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

power optimization techniques floorplanning Multiple Projects fast-paced process nodes Signal Integrity Leadership Skills EDA Tools Timing Closure design teams Placement dynamic environment Physical Design Implementation problem-solving skills communication Clock Tree Synthesis routing Static Timing Analysis

a month ago

MTS Silicon Design Engineer

Permanent Job

India

7-9 years

RTL Synthesis IP integration Timing Analysis EM Dual Patterning Ir analytical establishing design methodology primetime circuit/logic simulation Placement DRC Design Compiler Power-plan LVS Cadence Genus computer organization tools for logic synthesis Layout Physical Verification CTS ICC2 clock and power gating techniques Synopsys Fusion Compiler Timing Closure Apache Redhawk FinFET Attention To Details scan stitching Place And Route floorplanning Schematics Problem Solving design optimization logic equivalence GDS2 architecture Extraction physical/timing/electrical quality Formal Equivalence final signoff Innovus PNR tools Mentor Graphics Calibre Crosstalk Analysis Floor-plan Physical Implementation Clock Tree Synthesis StarRC Routing

a month ago

Silicon CAD/EDA/Methodology Lead, Google Cloud

Permanent Job

Bengaluru / Bangalore ,

India

8-14 years

TPU architecture floorplanning Physical Design AI/ML Verification hardware electronic design automation tools EDA flow sign-off Chip Design C++ Software Automation Python

a month ago

Silicon CAD EDA Methodology Lead, TPU Google Cloud

Permanent Job

Bengaluru / Bangalore ,

India

8-14 years

Chip Design hardware electronic design automation tools AI/ML Physical Design sign-off floorplanning Python C++ Software Automation

a month ago

Senior Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-10 years

CTS floorplanning SoC Physical design ICC/Innovus SoC STA Interpersonal Skills technology nodes Problem-solving IR Drop Analysis Physical Verification Extraction Placement Signal Integrity closure Timing Power Routing

4 months ago

Technologist, ASIC Development Engineering - Physical Desing Lead

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design Implementation fast-paced EDA Tools process nodes problem-solving skills Placement floorplanning power optimization techniques communication Signal Integrity design teams dynamic environment Multiple Projects Timing Closure Leadership Skills Clock Tree Synthesis Static Timing Analysis routing

4 months ago

Technologist, ASIC Development Engineering

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Sta Rtl Design Dft PPA Optimization floorplanning Verification Physical Design Eda

3 months ago

ASIC Physical Design, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

3-5 years

Design Compiler Dfm ICC/ICC2/FC formal verification clock tree optimization Dft low-power design CAD automation methods physical implementation synopsys tools Extraction Physical Synthesis IC design CAD high speed clock design and distribution floorplanning Physical Compiler Primetime SI Hercules/ICV Physical Verification Signal Integrity Hspice Timing Constraints Star-RCXT Timing Closure high-speed design routing Python Perl Tcl

5 months ago

A&MS Layout Design Engr, Sr I

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

LPE DDR/HBM IP layout automation top level verification flow Dfm written communication skills CMOS 28nm bondpad layout Scripting skills Esd Verification latchup layout design considerations IO frame mitigation Place & Route IR considerations Analog Mixed-signal layout digital flow IO abutment rules Strategies process technology LEF generation ASIC physical design flow EM DRC/LVS pitch requirements power rail routings Advanced floorplanning techniques high-speed digital Deep submicron effects Advanced tool usage Verbal Communication Skills FinFET layouts

5 months ago

SR Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

power analysis Advanced Node RTL Physical Design low power/multi-voltage physical implementation CAD automation methods floorplanning Timing ASIC implementation DRC closure DRC/LVS Logic Synthesis Placement Parasitic Extraction equivalence checking GDSII Design Methodologies Clock Tree Synthesis static timing analysis routing Python data preparation Perl Tcl

5 months ago

Layout Design, Sr Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

5 months ago

Layout Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-10 years

Analog Mixed-signal layout IO abutment rules IR considerations top level verification flow Place & Route EM DDR IOs customers CMOS power rail routings bondpad layout DRC/LVS coordination activities mitigation Process Verification development teams floorplanning techniques ASIC physical design flow FinFET layouts Dfm Remote site interaction written communication skills Digital IO frame layout automation LPE Deep submicron effects LEF generation Esd Scripting skills pitch requirements Verbal Communication Skills Technical Leadership

5 months ago

Senior Design Engineer - Physical Design

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

Extraction PPA high-speed interfaces floorplanning Asic Physical Design Cadence Full chip Physical Design Signal Integrity clock distribution solutions IR Drop Analysis primetime Design Timing Primetime-SI ASIC fundamentals P&R Synopsys problem-solving skills PERL Static Timing Analysis Scripting Languages Tcl

4 months ago

Senior Physical Verification Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

Sta Memory CTS Place & Route Analytical Skills Problem-solving Rtl Design Physical Verification Dft Attention To Detail GDS generation Validation Synthesis AMS verification floorplanning LEC RF layout design Layout Design SoC/subsystem integration and verification IP verification Functional Verification Good Manufacturing Practice (GMP) Chip Integration partitioning Debugging Analog

5 months ago

A&MS Layout Design Engr

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

5 months ago

A&MS Layout Design Engr, II

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

tool usage Analog Mixed-signal layout floorplanning techniques process technology latch-up layout design considerations ownership layout co-ordination activities written communication skills CMOS Remote site interaction Esd Verification Deep submicron effects high-speed SerDes IPs mitigation Accountability Verbal Communication Skills FinFET layouts development teams

5 months ago

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Floorplanning Jobs

Technical Staff Engineer - Physical Design

Physical Design - Engineer

Principal Engineer, ASIC Development Engineering (Physical Design)

Technologist, ASIC Development Engineering (Physical Design)

Senior Physical Design Engineer

Principal Engineer - Physical Design

Silicon CAD EDA Methodology Lead, TPU Google Cloud

Senior Physical Design Engineer

Physical Design Engineer

Principal Engineer, ASIC Development Engineering (Physical Design)

MTS Silicon Design Engineer

Silicon CAD/EDA/Methodology Lead, Google Cloud

Silicon CAD EDA Methodology Lead, TPU Google Cloud

Senior Physical Design Engineer

Technologist, ASIC Development Engineering - Physical Desing Lead

Technologist, ASIC Development Engineering

ASIC Physical Design, Sr Engineer

A&MS Layout Design Engr, Sr I

SR Application Engineer

Layout Design, Sr Engineer

Layout Design Engineer

Senior Design Engineer - Physical Design

Senior Physical Verification Engineer

A&MS Layout Design Engr

A&MS Layout Design Engr, II