Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience in ASIC/SoC development.
- Experience with ASIC design verification, synthesis, timing analysis.
- Experience handling Low Power schemes, power roll up, and power estimations.
Preferred qualifications:
- Experience with programming languages (e.g., Python, C/C++, or Perl).
- Experience with power optimization and power modeling tools.
- Experience in SoC designs and integration flows, with knowledge of high performance and low power design techniques.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
You will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with performance, power, and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design, and more to specify and deliver high quality designs for next generation data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Understand Power management schemes and Low Power modes for SoC and subsystems.
- Create power and UPF definition for SoC and Subsystems.
- Manage power estimation, roll up, and tracking through all phases of the project.
- Drive Power optimization tools and suggest ways to improve power.
- Work with cross-functional teams for hand-off of power intent and power projections.
