Work From Home Asic Verification Jobs

VLSI Manager/Director - India

Permanent Job

Pune ,

India

15-17 years

LINT cdc Reusable Testbench Architecture RTL modular Third Party IP Uvm Security Controllers video standards Synthesis ASIC SERDES C/C++ PHY LEC Verification Switching Digital Signal Processing Filters EDA Tools Processors dpi Networking Pcie Verilog Tcp/ip Static Timing Analysis System Verilog Python Automation Mac Ethernet Tcl Systemc

21 days ago

Sr Staff Engineer - Design Verification

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

test bench development Simulation verification plans ASIC design methodology Uvm Specman-e Tcl Scripting Ovm Unix Shell Scripting Perl Debugging System Verilog Systemc

20 days ago

Hardware Engineering Intern, Winter 2025 (English)

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Hardware System Verilog coding design concepts Verilog/HDL EDA Tools Design Verification computer hardware architecture SoC/ASIC Design Physical Design Design For Testability Methodology Electrical Engineering low power reduction techniques Scripting Languages

a month ago

Hardware Engineering Intern, Winter 2025 (English)

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

a month ago

Layout Design, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

LPE layout automation top level verification flow Dfm written communication skills CMOS latchup layout design high-speed digital layout bondpad layout Scripting skills Esd IO frame Place & Route IR considerations digital flow IO abutment rules process technology LEF generation ASIC physical design flow EM DRC/LVS layout co-ordination activities pitch requirements Analog Mixed-signal DDR/HBM IP layout power rail routings Remote site interaction Advanced floorplanning techniques Deep submicron effects Advanced tool usage Verbal Communication Skills FinFET layouts Technical Leadership

4 months ago

Layout Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-10 years

Analog Mixed-signal layout IO abutment rules IR considerations top level verification flow Place & Route EM DDR IOs customers CMOS power rail routings bondpad layout DRC/LVS coordination activities mitigation Process Verification development teams floorplanning techniques ASIC physical design flow FinFET layouts Dfm Remote site interaction written communication skills Digital IO frame layout automation LPE Deep submicron effects LEF generation Esd Scripting skills pitch requirements Verbal Communication Skills Technical Leadership

5 months ago

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Work From Home Asic Verification Jobs

VLSI Manager/Director - India

Sr Staff Engineer - Design Verification

Hardware Engineering Intern, Winter 2025 (English)

Hardware Engineering Intern, Winter 2025 (English)

Layout Design, Staff Engineer

Layout Design Engineer