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220
Vhdl Jobs
Senior Manager, Application engineering
Synopsys Inc
Permanent Job
Noida
,
India
13-15 years
LINT
LRM knowledge
HDLs
Uvm
Clock/Reset Domain Crossing
VHDL
Digital Design
verification technologies
Synopsys EDA tools
Simulation
SVA
UNIX
Verilog
System Verilog
Tcl
5 months ago
R&D Engineering, Sr Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-4 years
VHDL HDL/RTL languages
FPGA prototyping tools
Digital Design
C/C++
graph algorithms
Windows/Unix
Verilog
data structures
5 months ago
R&D Engineering, Sr Staff Engineer
Synopsys Inc
Permanent Job
Noida
,
India
0-2 years
ASIC design flow
distributed code development
data-structures
systemverilog
VHDL
EDA Tools
Unix/Linux platforms
C/C++
multi-threaded
Algorithms
Perl
Verilog
Tcl
5 months ago
Senior FPGA Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
3-5 years
quartus
Synthesis
VHDL
Vivado Analyzer
Xilinx
FPGAs
Altera
FPGA architecture
Verilog
5 months ago
Applications Engineer, Sr II
Synopsys Inc
Permanent Job
Noida
,
India
5-7 years
Verdi
LRM
make
Uvm
spyglass
VHDL
Simulation
SVA
VC SpyGlass
Shell Scripting
UNIX
Perl
Verilog
System Verilog
Tcl
5 months ago
R&D Engineering, Architect
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
Sat
Distributed processing
solver algorithms
formal verification
VHDL
heuristics
synthesis techniques
Algorithms
Bdd
Machine Learning
C
C++
Verilog
data structures
Big Data
System Verilog
5 months ago
R&D Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Noida
,
India
0-2 years
production code development
data-structures
systemverilog
distributed
VHDL
ASIC
C/C++
multi-threaded
Algorithms
Unix
Eda
Perl
Linux
Verilog
Tcl
5 months ago
ASIC Digital Verification Engineer, SrII
Synopsys Inc
Permanent Job
Noida
,
India
5-7 years
TCSH
VHDL
Uvm
systemverilog
PERL
Verilog
Bash
PYTHON
Tcl
5 months ago
R&D Engineering, Principal Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
Verdi
UVM-AMS
Custom IC Design
circuit simulation tools
VHDL-AMS
CAD
transistor-level simulation
UPF
AMS Verification
Verilog-AMS
System-Verilog
Vcs
5 months ago
Field-Programmable Gate Arrays Engineer
Tonbo Imaging pvt LIMITED
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
Intel Quartus
Verbal Communication
Xilinx Vivado
Problem-solving
VHDL
Written Communication
HDMI
Questa
Modelsim
collaborative team environment
Image Processing
Dsp
Fpga
Hdl
Pcie
Verilog
Ethernet
5 months ago
Applications Engineer
Synopsys
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
VHDL
Digital Design
HDLs
System Verilog assertions
Scripting Language
Eda
Verilog
System Verilog
UNIX
Tcl
5 months ago
Design Automation Engineer with PDK Expertise
UniHire
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
3-5 years
cd
VHDL
Eda
Verilog
Ci
Python
Tcl
4 months ago
Staff Engineer, Verification
Marvell Semiconductors
Permanent Job
Bengaluru / Bangalore
,
India
7-9 years
CVS
AMS simulation
Simulation Tools
regression mechanisms
High Speed SerDes
Cadence
Uvm
VHDL
PHYs
configuration management system
Asynchronous clock domain crossing verification
IP architecture
systemverilog
specification
Gatelevel simulation
digital logic
test-bench development
clock data recovery
Hardware Verification
Ovm
Svn
Verilog
automation
Scripting Languages
Perl
Linux Operating System
Bug Tracking
4 months ago
FPGA Design Engineer
Altiostar, A Rakuten Symphony Company
Permanent Job
Bengaluru / Bangalore
,
India
10-20 years
PDSCH
DDC
Simulink
IFFT
CFR
DUC
VHDL
FFT
JESD204
Modelsim
PUSCH
AGC
beamforming
PRACH
O-RAN
quartus
Vivado
DPD
CPRI
Fpga
Verilog
Dsp
Ethernet
Matlab
4 months ago
FPGA Principal Engineer
Thales
Permanent Job
Bengaluru / Bangalore
,
India
15-17 years
CVS
LVDS/Video
arinc 429
RTL
MILSTD 1553
Synthesis
RS-232
VHDL
RS-485/422
Subversion (SVN)
DO-254 Process assurance
Questasim
make
Formal Pro
HDL Designer
Quest CDC
P&R
Fpga
Shell Scripts
Pcie
Verilog
Python
Git
Perl
Ethernet
5 months ago
CPU RTL Power management Design Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
VHDL
Timing
microprocessor architecture
Power
logic design principles
Perl
Verilog
Python
5 months ago
Low Power Staff Applications Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
VC LP
Verdi
systemverilog
VHDL
ASIC
VC Formal
VC SpyGlass
Eda
python
C
Verilog
Tcl
5 months ago
R&D Engineer II
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
1-4 years
ASIC flows
Design for Test
Rtl Design
spyglass
VHDL
frontend digital design
EDA Tools
C/C++
perl
System Verilog
Verilog
Python
Tcl
5 months ago
R&D Engineer, Architect
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
15-18 years
Sat
Distributed processing
solver algorithms
formal verification
VHDL
heuristics
synthesis techniques
Algorithms
Bdd
Machine Learning
C
C++
Verilog
data structures
Big Data
System Verilog
5 months ago
CPU RTL Power Design Engineer - Sr Lead
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-4 years
RTL power estimation
low power devices
HW throttling mechanisms
CPU performance
peak current limits
logic design principles
CPU power modeling
CPU RTL Power
energy efficient CPU designs
VHDL
low power minimization techniques
Scripting Language
Tdp
EDP
Perl
Verilog
Python
5 months ago
CPU RTL Power Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-8 years
low power design
PowerArtist
RTL
fast-paced
Problem Solving
logic design principles
battery life projections
VHDL
ASIC
dynamic environment
Organizational Skills
low power minimization techniques
Communication Skills
Scripting Language
Cpu
Perl
Verilog
Python
5 months ago
R&D Engineer II
Synopsys Inc
Permanent Job
Noida
,
India
1-4 years
ASIC flows
Design for Test
Rtl Design
spyglass
VHDL
frontend digital design
EDA Tools
C/C++
perl
System Verilog
Verilog
Python
Tcl
5 months ago
staff engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
Verilog/VHDL RTL level designs
gprof
timing constrains
FPGA prototyping
purify
C/C++ programming
EDA software
graph algorithms
static timing analysis
Digital Logic Design
Coverity
data structures
5 months ago
R&D Engineering, Architect
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
Sat
Distributed processing
solver algorithms
formal verification
VHDL
heuristics
synthesis techniques
Algorithms
Bdd
Machine Learning
C
C++
Verilog
data structures
Big Data
System Verilog
5 months ago
R&D Engineering, Sr Staff Engineer
Synopsys Inc
Permanent Job
Noida
,
India
0-2 years
production code development
data-structures
systemverilog
distributed
VHDL
ASIC
C/C++
multi-threaded
Algorithms
Unix
Eda
Perl
Linux
Verilog
Tcl
5 months ago
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