Verification Ip Jobs in Pune

IP Verification Manager

Permanent Job

Pune ,

India

10-12 years

TCSH VHDL Uvm systemverilog PERL Verilog Bash PYTHON Tcl

4 days ago

LINT cdc Reusable Testbench Architecture RTL modular Third Party IP Uvm Security Controllers video standards Synthesis ASIC SERDES C/C++ PHY LEC Verification Switching Digital Signal Processing Filters EDA Tools Processors dpi Networking Pcie Verilog Tcp/ip Static Timing Analysis System Verilog Python Automation Mac Ethernet Tcl Systemc

17 days ago

Pre - Silicon Validation

Permanent Job

Remote ,

India

8-12 years

CPU Verification processor Memory analytical validation content Uvm Graphics Video RTL validation Design system simulation models architecture validation platforms staging Audio verification test plans validation coverage display Ip Problem Solving test bench infrastructure AMBA Axi feature scoping Pre-Si validation AHB C Ovm Debugging System Verilog C++ Soc Pci

5 months ago

Digital Verification ASIC Engineer

Permanent Job

Delhi ,

Hyderabad / Secunderabad, Telangana ,

Bengaluru / Bangalore ,

Chennai ,

Kolkata ,

Mumbai ,

Pune ,

India

7-9 years

Asic verification design for re-use of pre and post silicon tests and infrastructure Uvm Ethernet MAC Security EDA Tools protocols C/C++ PHY Switching video standards modular and reusable testbench architecture automation of testbench creation tests digital signal processing filters third party IP Regression Processing dpi Pcie Verilog Tcp/ip System Verilog Python Tcl Systemc

5 months ago

Design Verification Engineer

Permanent Job

Ahmedabad ,

Pune

4-8 years

SOC/IP Verification System Verilog/UVM RTL

5 months ago

Analog Layout Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

Bengaluru / Bangalore ,

Noida ,

Pune ,

India

0-2 years

analog layout techniques speed Proactive Problem-solving Leadership ERC Power noise Delivery CMOS lpe bandgap circuit principles differential amplifier bi-cmos Pll comparator Layout Design pnr flow Timing Closure mentor eda tools ldo Mentor phy Antenna soi drc virtuosoxl communication guide adc Mixed Signal finfet cts ref generators current mirrors capacitance area HDMI LVS ams ip integration Dfm Cadence Physical Verification SERDES team members Custom Layout charge pump routing Quality Dac Analog

5 months ago

Principal Design Engineer

Permanent Job

Pune ,

India

8-12 years

sub-micron technology Ip Quantus Verbal Communication Tempus Physical Design Physical Verification Innovus formal verification ASIC Written Communication Timing Closure Cadence implementation tools Genus Tk hierarchical physical design EM-IR Makefile Soc Pvs Perl Tcl

5 months ago

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Verification Ip Jobs in Pune

IP Verification Manager

VLSI Manager/Director - India

Pre - Silicon Validation

Digital Verification ASIC Engineer

Design Verification Engineer

Analog Layout Engineer

Principal Design Engineer