Transistor Level Design Jobs

Memory Design Verification Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

transistor level simulations Skill/Perl/Python Scripting signal integrity analysis Monte Carlo variation analysis Cadence schematic/layout editor tools EM/IR analysis/simulations QA and validation checks waveform viewer tools automation scripts memory design verification

a month ago

Circuit design Std cell & characterisation

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Data Analysis Cadence transistor-level standard cell library design FinFET technology Problem-solving Layout Design Cadence Virtuoso Liberate/LV/Mx/Trio circuit-level simulations power analysis methodologies characterization Synopsys Circuit Design advanced process nodes Eda static timing analysis

3 months ago

Senior Staff RTL Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

transistor-level circuit design software Microsoft Office Suite Perl Linux Python

3 months ago

R&D Engineering, Principal Engineer

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

Verdi UVM-AMS Custom IC Design circuit simulation tools VHDL-AMS CAD transistor-level simulation UPF AMS Verification Verilog-AMS System-Verilog Vcs

5 months ago

Analog Design Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

10-12 years

switching global products CMOS DACs bicmos Systems Design Power architecture LDOs Debug bandgap Team Control ADCs Packaging capacitor Layout Management Application Process transistor Product Schedule references project DMOS Manager Supply Passion reviews Written Mixed-signal mode Ic ics Validation communication Circuits large Level BCD tradeoffs Test Development prediction Oscillators Verbal Engineering Analysis feasibility Amplifiers switch-mode regulator switched managers Switch Conversion Reports Topologies Technologies Analog

5 months ago

A&MS Circuit Design Engr, Sr II

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

6-8 years

Ultrasim Cadence layout effects ESD issues HSIM custom design amplitude transistor level circuit design noise communication signal integrity issues system level budgeting Documentation custom digital design Packaging SERDES sub circuits post processing of simulation results jitter board parasitics Hspice Design for reliability crosstalk Analog Design Scripting

5 months ago

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Transistor Level Design Jobs

Memory Design Verification Engineer

Circuit design Std cell & characterisation

Senior Staff RTL Design Engineer

R&D Engineering, Principal Engineer

Analog Design Engineer

A&MS Circuit Design Engr, Sr II