587

Tcl Jobs

Sr. Staff Digital Engineer, Synthesis and STA

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

LINT power analysis Synthesis cdc UPF Design Compiler Digital Design Timing Constraints formality tweaker EDA prime time Perl Python Tcl

27 days ago

Sr. Staff Digital Engineer, Synthesis and STA

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

LINT power analysis Synthesis cdc UPF Design Compiler Digital Design Timing Constraints tweaker EDA tool sets formality prime time Perl Python Tcl

27 days ago

Sr. Principal Software Engineer

Permanent Job

Noida ,

India

10-15 years

C/C++ VHDL algorithmic language compiler Data Structure Tcl UNIX System Verilog LINUX

22 days ago

Engineer II,QA

Permanent Job

Bengaluru / Bangalore ,

India

1-3 years

5G NR TM500 ORAN Channel Emulator PHY/ Stack algorithms Ran Lte Tcl Python Qxdm 3gpp

26 days ago

Sr. Principal Software Engineer

Permanent Job

Noida

10-15 years

VHDL language compiler C/C++ algorithmic LINUX UNIX System Verilog Tcl Data Structure

22 days ago

Sr. Engineer - Physical Design

Permanent Job

Noida ,

India

6-12 years

Floor Planning Timing Closure Synopsys Physical Design Cadence Clock Tree Synthesis routing python perl Tcl

24 days ago

Engineer II,QA

Permanent Job

India

1-3 years

5G NR ORAN wireless test tools PHY/ Stack algorithms Lte Tcl automation Python Scripting 3gpp

27 days ago

Design Verification Engineer |4 to 15 Yrs | Bangalore,Hyderabad,Noida

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

Fresher

UVM/OVM Protocols AHB/AXI/APB IP Verification GLS Emulation LPDDR SoC Verification SV AMs Mipi CSI/DSI LEC Functional coverage Test bench / model / VIP development Spi Shell Pcie Verilog I2c Python Usb Can Perl Ethernet Arm Tcl

25 days ago

Sr. Manager Silicon Design Engineering

Permanent Job

Bengaluru / Bangalore ,

India

18-20 years

Sta Verilog RTL design Physical Design timing signoff Shell Perl Constraints Python Tcl

24 days ago

Sr. Manager Silicon Design Engineering

Permanent Job

India

18-20 years

Sta Physical Design Verilog RTL design timing signoff Tcl Constraints Python Perl Shell

27 days ago

Staff/Sr Staff STA Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-8 years

Sta Full flow Implementation tools Verilog/SV Fusion Compiler Digital Design methodologies Simulation RTL static timing analysis concepts UPF primetime spyglass Synthesis RTL Coding CAD automation methods Synopsys Design Compile GDSII Perl Python Tcl

a month ago

Lead/Senior/Junior Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

Synthesis lpc mmmc rf layout design AMs innovus lec Physical Verification PNR ERC icc2 pt sta low power fixes perl Tcl

a month ago

Senior Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-15 years

Sta CTS Chip finishing floorplanning Power Integrity Analysis PnR Suite Advanced Physical Verification Techniques Physical Verification Tcl/Tk/Perl Low Power Placement Netlist2GDSII Implementation SOC integration EM/IR-Drop analysis Power Grid Design high speed design Routing Static Timing Analysis

a month ago

STA Engineers

Permanent Job

Noida ,

India

0-2 years

semiconductor design projects team environment EDA Tools Electrical Engineering Computer Science Analytical Skills Problem-solving Perl Static Timing Analysis Tcl

a month ago

Engineer II - Validation

Permanent Job

Chennai ,

India

3-5 years

NI Tools test stand Assembly Language Usb Uart Spi Can Timers Perl Ethernet C Programming Language I2c Python Tcl LabVIEW

a month ago

Physical Design Engineer

Permanent Job

Noida ,

India

1-3 years

ASIC RTL Eda Fpga Perl Python Tcl

a month ago

IC Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

Dc Pt Quantus Tempus Voltus Innovus Star-RCXT Genus PrimeRail Eda Perl Tcl

a month ago

CAD Automation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-5 years

rulesets Custom flows automation ICManage PDK evaluation tool License features OA Productivity license administration Device Modeling DEF LIB LEF Simulation environment C-Shell scripts Schematic entry EMIR Layout Design 4nm DRC Simulation Methodics Custom Design Automation Customer rule deck customizations post layout simulation Analog cell characterization Foundry Electrical verification Reliability Verification 10nm Job submission LVS CDL Analog/Mixed-signal Design Cliosoft Gds SPEF Efficiency Methodologies Tapeouts Spice Monitoring Physical Verification Parasitic Extraction interfacing Deep Submicron Issues/technologies chip finishing runs 3nm 14nm 5nm 7nm scripting skills EDA Tools finfet technologies Svn PERL Perforce Verilog Data Management Python Git Tcl

a month ago

Senior Engineer II - Layout Design

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

Cadence Tools blocks and macros layout analog layout concepts ICV verification tools Analog Layout low parasitic EMIR high frequency design techniques PERC tools Synopsys Finfet process Tcl Scripting

a month ago

Software Developer 4

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

10-12 years

H.323 IP Security Technologies VoIP Volte SIP Java Ims Rcs Networking Python Tcl

a month ago

Automation Test Engineer (2-5 years)

Permanent Job

Chennai ,

India

2-4 years

best practices CI/CD QA principles PACT IBM Jazz Playwright Cypress cross platform product verification E2E testing frameworks TestCafe Robot Methodologies Javascript JIRA Selenium Testing Gitlab Tcl Postman Python release management Perl Agile Software Development Configuration

a month ago

Synthesis Engineer

Permanent Job

Noida ,

India

1-2 years

Synthesis LP signoff tools LEC Fusion Compiler VHDL QoR optimization Genus Regression Equivalence Checking Python Configuration Management Version Control Tcl Verilog

a month ago

STA/ Timing Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-4 years

Sta monte carlo multi-cycle ICC Model device Innovous signal reviews cross-talk Hspice silicon ASIC FEED through Integrity Tempus multi-mode Extraction physics AOCV RTL multi-voltage Pt noise Digital transparency Handling CTS 0-cycle Layout Parasitic signoff Spice back-end path Latch Gds convergence POCV FineSim Correlation Tcl Perl Python

30 days ago

STA/Timing Methodology Sr Engineer

Permanent Job

Noida ,

India

1-2 years

spyglass Digital Hardware Optical Rf PNR Extraction Fpga Dsp Tcl Python Perl Analog

a month ago

PnR Implementation Staff Engineer

Permanent Job

Noida ,

India

2-9 years

CMOS technology Fusion compiler Physical Verification Place And Route physical design concepts CTS Innovus flooplanning STA analysis PnR Implementation Tcl Perl python

a month ago

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tcl Jobs

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Tcl Jobs

Sr. Staff Digital Engineer, Synthesis and STA

Sr. Staff Digital Engineer, Synthesis and STA

Sr. Principal Software Engineer

Engineer II,QA

Sr. Principal Software Engineer

Sr. Engineer - Physical Design

Engineer II,QA

Design Verification Engineer |4 to 15 Yrs | Bangalore,Hyderabad,Noida

Sr. Manager Silicon Design Engineering

Sr. Manager Silicon Design Engineering

Staff/Sr Staff STA Engineer

Lead/Senior/Junior Design Engineer

Senior Physical Design Engineer

STA Engineers

Engineer II - Validation

Physical Design Engineer

IC Design Engineer

CAD Automation Engineer

Senior Engineer II - Layout Design

Software Developer 4

Automation Test Engineer (2-5 years)

Synthesis Engineer

STA/ Timing Engineer

STA/Timing Methodology Sr Engineer

PnR Implementation Staff Engineer