570

Tcl Jobs

Verification Engineer or Senior Verification Engineer SOC

Permanent Job

Bengaluru / Bangalore ,

India

1-3 years

analytical EDA design verification tools RISC-V MIPS CPU Problem-solving formal verification reference model-based checkers functional safety flows constrained random generators Assembly systemverilog functional verification methodologies digital design concepts Interconnect protocols coherency CPU verification C multi-core Shell Verilog Python C++ Perl Arm Tcl

12 days ago

Digital Designer

Permanent Job

Bengaluru / Bangalore ,

India

8-9 years

DV verifications Mentor effort AMS methodologies regulators DACs switched cap circuits Verilog-D SV-RNM Verilog-A Mentoring Junior engineer Digital SV project dynamics Rtl Coding Styles analog circuit basics ADCs optimization of simulation bench MSV Skill charge pumps Eldo ADMS simulation time Verilog-AMS verification for IPs Analog Design multi-site development environment Synopsys Schedule alternative verification plans op-amps Verilog Hdl Cadence project team UVM testbench development proposing new scenarios analog and mixed signal building blocks AMS simulation environment Comparators current mirrors Real xrun mixed signal perspective irun Testcase Debug AMS Verification XA-VCS product specifications behavioral modeling Scope Scripting Python Test Plan Preparation Analog Perl Tcl

7 days ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-5 years

cdc Mentor Calibre project management continuous learning Fusion Compiler analytical Collaborative Cadence Innovus Physical Design Problem-solving EDA Tools Innova"s Cadence Si ics Synopsys Synopsys ICC2 communication Eda Perl Pi Python Tcl

13 days ago

Principal engineer SoC connectivity

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

Coordination Software MS-Office mixed signal semiconductors VHDL microcontroller products code checkers communication SV-Verilog Window Efficiency IFX internal tooling chip level connectivity development team IC design Methodologies Quality Checks English Simulators service/debugging/bug fixing power concept Java Perforce C PYTHON Workflow programming Scripting Clearcase Soc Architecture UNIX Git Tcl

14 days ago

Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

2000000 - 2600000 INR

Place & Route Functional Safety Synthesis Physical Design Timing Closure RTL Coding FINFET technologies Programming Skills Perl Scripting Languages Python Tcl

13 days ago

Principal Engineer - Physical Design

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

place-and-route power network planning Vlsi EM/IR analysis analytical Reliability system-level floorplanning low-power design methodologies Innovus Calibre Leadership Skills redhawk Timing Closure Interpersonal Abilities Communication Skills Clock Tree Synthesis power integrity Perl scripting Debugging Logic Design Tcl

11 days ago

Staff SOC Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

Place & Route Synthesis Physical Design Timing Closure RTL Coding FINFET technologies Functional Safety Perl Python Tcl

13 days ago

Principal Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

14-16 years

Sta Integrated Package Cadence Mentor Dfm Innovus Calibre Physical Verification Partitioning EDA Tools Floor Planning DFY Clock Tree Synthesis Clock Planning Pin placement Tapeout Parasitic Extraction Eco Physical Design Timing Closure Die size analysis Power Plan Analog IP Integration Place And Route Synopsys Python Scripting Tcl

13 days ago

Vehicle Durability Simulation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-6 years

Hypermesh radioss Ansys Mechanical Strength Of Materials ABAQUS Nonlinearities FEMFAT Hyperworks Optistruct Tcl-tk Dynamics Theory of Machine HyperStudy LS-Dyna Fatigue Solvers Python

8 days ago

Principal DFT Engineer

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

test insertion scan compression 1149.1 digital ASIC front and backend design & verification processes Cadence Unix/Linux environments at-speed testing Synthesis 3DIC logic bist Verification Siemens 1838 supporting silicon into volume production IJTAG Memory BIST Debug test pattern development IEEE standards such as 1500 SSN Designing conducting experiments/tool evaluations 1687 Functional Safety as it applies to DFT Siemens MBIST and LBIST tools current mobile SOC architectures and low power design practices test coverage assessment Synopsys DFT tools Fault Simulation Static Timing Analysis (STA) Jtag Perl C Programming Tcl

11 days ago

Principal PPA Solutions Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

VLSI CAD Software distributed processing Physical Design EDA tool-flows Timing Power C Data Analytics Disk Management Dashboards Version Control Systems automation metrics Python Tcl

13 days ago

Emulation Eniginner

Permanent Job

Bengaluru / Bangalore ,

India

4-12 years

transactors Palladium RTL flash memories SV-UVM/C Arm CPU cores AMBA UART/SPI/I2C ZeBu Veloce Usb Unix Shell Scripting DDR Pcie Perl Ethernet Tcl

12 days ago

High Speed IO Validation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

Silicon manufacturing jitter lab/measurement equipment USB3 PCIe-gen5 DDRx Signal Integrity Thunderbolt SAS Perl Python Tcl

7 days ago

High Speed IO Validation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

power analysis Timing Analysis driver structures high speed interfaces HW BER HSIO EE fundamentals process variations statistical error rates Automation Scripting Usb Pcie Perl Linux Computer Architecture Firmware Python Tcl

7 days ago

RTL Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

UVM (Universal Verification Methodology) Clock Domain Crossing (CDC) analysis formal verification techniques systemverilog Rtl Design VHDL Cadence Lint EDA Tools Verification RTL lint tools Synopsys Lint Communication Skills Verilog Python Tcl

7 days ago

Staff CAD Engineer

Permanent Job

Pune ,

India

7-10 years

GenAI RTL Tempus Innovus spyglass Genus virtuoso HW revision control GDSII Lsf Eda shell scripting Tcl

7 days ago

Senior Engineer - FPGA Verification

Permanent Job

Bengaluru / Bangalore ,

India

3-6 years

NanoXplore Xmap ALTERA Libero SoC XILINX Vivado Oscilloscope Logic Analyzer DO-254 RTL Questasim Formal Pro altera quartus GLS HDL Designer Quest CDC VHDL Mentor Graphics Function Generators In-circuit de-buggers Fpga Doors Jtag Perl Python Tcl

10 days ago

DFT Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

1149.1 Memory BIST analytical systemverilog boundary scan Problem-solving 1500 1687 ICL VHDL Tessent revision control mechanisms Collaboration Verilog-AMS Scan pdl IJTAG communication Jtag Perl Verilog Python Tcl

9 days ago

R&D Software Engineer - LLM, Generative AI

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

Formal Technologies digital logic C/C++ Equivalence Checking Algorithms Eda Cloud Technologies Containers data structures Python Kubernetes Tcl

14 days ago

Test & Validation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

1-2 years

525000 - 600000 INR

synopsys primetime Perl Static Timing Analysis Python Tcl

7 days ago

IP Verification Manager

Permanent Job

Pune ,

India

10-12 years

TCSH VHDL Uvm systemverilog PERL Verilog Bash PYTHON Tcl

7 days ago

Internship in Functional Verification

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Computer Memory Organization C/C++ Perl shell scripting Verilog Oo Programming System Verilog Tcl

14 days ago

R&D Engineering, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-5 years

Object-Oriented Programming Uvm Verilog Shell Scripting System Verilog Python Tcl

11 days ago

Analog Design, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

reference circuits clock generators simulation methodologies Hspice Amplifiers design verification efficiency Custom Analog Design Primesim analog circuit building blocks Vcs Perl Python Tcl

11 days ago

Test & Validation Engineer

Permanent Job

Bengaluru / Bangalore ,

India

1-2 years

525000 - 600000 INR

synopsys primetime Perl Static Timing Analysis Python Tcl

7 days ago

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Tcl Jobs

Verification Engineer or Senior Verification Engineer SOC

Digital Designer

Physical Design Engineer

Principal engineer SoC connectivity

Staff Engineer

Principal Engineer - Physical Design

Staff SOC Engineer

Principal Physical Design Engineer

Vehicle Durability Simulation Engineer

Principal DFT Engineer

Principal PPA Solutions Engineer

Emulation Eniginner

High Speed IO Validation Engineer

High Speed IO Validation Engineer

RTL Design Engineer

Staff CAD Engineer

Senior Engineer - FPGA Verification

DFT Engineer

R&D Software Engineer - LLM, Generative AI

Test & Validation Engineer

IP Verification Manager

Internship in Functional Verification

R&D Engineering, Staff Engineer

Analog Design, Staff Engineer

Test & Validation Engineer