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6
Static Timing Analysis Jobs in Delhi
STA Engineers
Mirafra Technologies
Permanent Job
Noida
,
India
0-2 years
semiconductor design projects
team environment
EDA Tools
Electrical Engineering
Computer Science
Analytical Skills
Problem-solving
Perl
Static Timing Analysis
Tcl
a month ago
Physical Design Engineer
Qualcomm Technologies, Inc
Permanent Job
Noida
,
India
1-2 years
PNR
Multi-point CTS
PnR tool knobs/recipes
PPA optimization
tackling high placement density/congestion bottlenecks
floorplanning
CTS
Placement & Optimization
Power Planning
H-tree
PG-Grid optimization
custom clock tree
Post route optimization
Adaptive PDN
spine
Clock metrics optimization
ECO implementation
DRC closure
Static timing analysis
Tcl
Routing
Python
Perl
4 months ago
STA/Timing Sign-off Engineer - Sr Lead
Qualcomm Technologies, Inc
Permanent Job
Noida
,
India
1-6 years
PD Implementation
High frequency Datapath intensive Cores
Electronics Engineering
Power Estimation
Computer Science
Primetime/Tempus
Rtl Design
ASICs
Synthesis
Dft
Physical Synthesis
Power teams
multi voltage design convergence
Tcl/Perl scripting
Constraint development
Static Timing Analysis (STA)
Clock Tree Synthesis
hardware engineering
4 months ago
STA/Synthesis Engineer
7Rays Semiconductors India Private Limited
Permanent Job
Noida
,
India
3-5 years
Sta
Logical aware Synthesis
CTS
constraint development
RTL design team
Sub system level
Timing Closure
PRO Clock gating checks
Synthesis
Logical Equivalence check
DMSA flow
Prelayout timing analysis
UNIX env
Placement
final tapaout timing closure
HMs team
Block level
Post layout timing analysis
Manual ECO
PD team
Tcl Scripting
Chip Level
Static Timing Analysis
4 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Noida
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Delhi
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
1
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