109

Static Timing Analysis Jobs

Senior Staff Engineer - Product Validation Engineer - STA Primetime

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

SDC constraints PBA timing Timing Analysis synopsys primetime distributed ECO flows derates Extraction advanced OCV concepts physical design closure Power hierarchical STA flows Perl Static Timing Analysis Python Tcl

a day ago

Senior Staff Engineer - Product Validation Engineer - STA Primetime

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

a day ago

Principal Digital Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-12 years

LINT systemverilog Design Verification cdc Logic Synthesis processor Stream protocols AHB formal equivalence APB Dft Axi power analysis Verilog Static timing analysis Dsp Soc Architecture

2 days ago

Senior Digital Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-8 years

LINT systemverilog Design Verification cdc Logic Synthesis processor Stream protocols AHB formal equivalence APB Dft Axi power analysis Verilog Static timing analysis Dsp Soc Architecture

5 days ago

Digital Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-4 years

LINT systemverilog Design Verification cdc Logic Synthesis processor Stream protocols DSP fundamentals AHB formal equivalence APB Dft Axi power analysis Verilog Static timing analysis Soc Architecture

5 days ago

SOC Implementation Lead - MTS Silicon Design Engineer

Permanent Job

India

0-2 years

Floor Planning physical design tools Upf signoff checks LVS primetime Calibre power optimization techniques Synopsys ICC2 Signal Integrity Timing Closure DRC PNR Redhawk-SC Tcl static timing analysis Python Perl

9 days ago

DFT Engineering Technical Lead :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

Dft P1687 Test Architecture primetime Scan Ate Gate level simulation Logic Equivalency Methodology Test Static Timing Analysis TestMax Post-silicon validation ATPG bist Infrastructure Tessent TetraMax Tcl Verilog System Verilog Jtag Perl Vcs Eda Python

13 days ago

Principal DFT Engineer

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

test insertion scan compression 1149.1 digital ASIC front and backend design & verification processes Cadence Unix/Linux environments at-speed testing Synthesis 3DIC logic bist Verification Siemens 1838 supporting silicon into volume production IJTAG Memory BIST Debug test pattern development IEEE standards such as 1500 SSN Designing conducting experiments/tool evaluations 1687 Functional Safety as it applies to DFT Siemens MBIST and LBIST tools current mobile SOC architectures and low power design practices test coverage assessment Synopsys DFT tools Fault Simulation Static Timing Analysis (STA) Jtag Perl C Programming Tcl

8 days ago

Test & Validation Lead Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

9 days ago

Technologist, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design Process Nodes EDA Tools power optimization Placement floorplanning Signal Integrity Routing Static Timing Analysis

11 days ago

Principal Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

Physical Design Implementation fast-paced EDA Tools problem-solving skills Placement floorplanning physical design flows power optimization techniques advanced process nodes communication Signal Integrity design teams dynamic environment Multiple Projects Timing Closure Leadership Skills Clock Tree Synthesis Static Timing Analysis routing

11 days ago

ASIC Digital Design, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

Synthesis Design Compiler digital fundamentals primetime high-speed protocol PHY ASIC Digital Design Formality TetraMax Proactive self-motivated Rtl Design English Dft spyglass Communication Skills Static Timing Analysis

10 days ago

Senior Staff Engineer - Test & Validation Engineer - STA Primetime

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

physical design closure Timing Analysis SDC constraints hierarchical STA flows ECO flows derates PBA timing synopsys primetime distributed Extraction advanced OCV concepts Power Static Timing Analysis Tcl Python Perl

8 days ago

Test & Validation Lead Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

9 days ago

Principal Digital Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-12 years

LINT systemverilog Design Verification cdc Logic Synthesis processor Stream protocols AHB formal equivalence APB Dft Axi power analysis Verilog Static timing analysis Dsp Soc Architecture

9 days ago

Senior STA (Static Timing Analysis) Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-10 years

Physical Design Closure Noise Delay Power Analysis Flow synopsys primetime Glitch Analysis Flow Flow Test & Validation Parasitic Extraction Flow Eco Debugging Perl Static Timing Analysis Python Tcl

a month ago

VLSI Manager/Director - India

Permanent Job

Pune ,

India

15-17 years

LINT cdc Reusable Testbench Architecture RTL modular Third Party IP Uvm Security Controllers video standards Synthesis ASIC SERDES C/C++ PHY LEC Verification Switching Digital Signal Processing Filters EDA Tools Processors dpi Networking Pcie Verilog Tcp/ip Static Timing Analysis System Verilog Python Automation Mac Ethernet Tcl Systemc

17 days ago

DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

16 days ago

Intern (Technical Engineering)

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

Rtl Design Synthesis Dft ASIC Digital Design Shell Static Timing Analysis Tcl

17 days ago

ASIC Digital Design, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

Rtl Design Synthesis Dft spyglass ASIC primetime Design Compiler/Formality DFT Tetramax static timing analysis

16 days ago

Senior IP Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-6 years

Synthesis Design Verification API-C RTL UCIe Verification front-end design formal verification ASIC HBM hardware debug DPI-C CXL mixed signal circuit design static timing analysis Silicon Validation DDR Pcie Ethernet Firmware

26 days ago

Staff/Sr Staff STA Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-8 years

Sta Full flow Implementation tools Verilog/SV Fusion Compiler Digital Design methodologies Simulation RTL static timing analysis concepts UPF primetime spyglass Synthesis RTL Coding CAD automation methods Synopsys Design Compile GDSII Perl Python Tcl

a month ago

Senior Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-15 years

Sta CTS Chip finishing floorplanning Power Integrity Analysis PnR Suite Advanced Physical Verification Techniques Physical Verification Tcl/Tk/Perl Low Power Placement Netlist2GDSII Implementation SOC integration EM/IR-Drop analysis Power Grid Design high speed design Routing Static Timing Analysis

a month ago

STA Engineers

Permanent Job

Noida ,

India

0-2 years

semiconductor design projects team environment EDA Tools Electrical Engineering Computer Science Analytical Skills Problem-solving Perl Static Timing Analysis Tcl

a month ago

Senior Staff Engineer - STA

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

STA methodologies CPU implementation Tcl Scripting Python Scripting Static Timing Analysis

a month ago

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Static Timing Analysis Jobs

Senior Staff Engineer - Product Validation Engineer - STA Primetime

Senior Staff Engineer - Product Validation Engineer - STA Primetime

Principal Digital Design Engineer

Senior Digital Design Engineer

Digital Design Engineer

SOC Implementation Lead - MTS Silicon Design Engineer

DFT Engineering Technical Lead :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Principal DFT Engineer

Test & Validation Lead Engineer

Technologist, ASIC Development Engineering (Physical Design)

Principal Engineer, ASIC Development Engineering (Physical Design)

ASIC Digital Design, Sr Engineer

Senior Staff Engineer - Test & Validation Engineer - STA Primetime

Test & Validation Lead Engineer

Principal Digital Design Engineer

Senior STA (Static Timing Analysis) Engineer

VLSI Manager/Director - India

DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Intern (Technical Engineering)

ASIC Digital Design, Sr Engineer

Senior IP Application Engineer

Staff/Sr Staff STA Engineer

Senior Physical Design Engineer

STA Engineers

Senior Staff Engineer - STA