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Fresher rtl verification jobs
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144
Rtl Verification Jobs
Senior Physical Verification Engineer
Excelmax Technologies
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Sta
Memory
CTS
Place & Route
Analytical Skills
Problem-solving
Rtl Design
Physical Verification
Dft
Attention To Detail
GDS generation
Validation
Synthesis
AMS verification
floorplanning
LEC
RF layout design
Layout Design
SoC/subsystem integration and verification
IP verification
Functional Verification
Good Manufacturing Practice (GMP)
Chip Integration
partitioning
Debugging
Analog
5 months ago
R&D Engineering, Sr Staff Engineer
Synopsys
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
Formality
RTL
Physical Verification
spyglass
spice output
Gds
timing signoff methodologies
TCL programming
ip development
Vcs
Qa
Git
5 months ago
ASIC Physical Design, Staff Engineer
Synopsys Inc
Permanent Job
Pune
,
India
5-7 years
analog/digital interfaces
Design Compiler
PERC
primetime
Fusion Compiler
FinFET
ICC2
RTL
Digital Design
LVS
Calibre
physical
timing analysis tools
architecture
CAD automation methods
timing signoff
Synthesis
physical verification tools
Place And Route
TSMC
implementation flows
Timing Constraints
ERC
DRC
low-power design techniques
ICV
GDSII
Python
Perl
Tcl
5 months ago
R&D Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
software specification
RTL Synthesis
analytical
Problem-solving
formal verification
design process
Compilers
synthesis techniques
Algorithms
C
C++
Regression Testing
UNIX
Linux
Debugging
data structures
5 months ago
Senior/Staff/Sr Staff Physical Design Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
7-15 years
Physical Verification
RTL
Physical Implementation
GDSII
Unix
Perl
Tcl
5 months ago
ASIC Physical Design Engr, Sr
Synopsys Inc
Permanent Job
Pune
,
India
5-7 years
analog/digital interfaces
Design Compiler
PERC
primetime
Fusion Compiler
FinFET
ICC2
RTL
Digital Design
LVS
Calibre
physical
timing analysis tools
architecture
CAD automation methods
timing signoff
Synthesis
physical verification tools
Place And Route
TSMC
implementation flows
Timing Constraints
ERC
DRC
low-power design techniques
ICV
GDSII
Python
Perl
Tcl
5 months ago
DFT engineer
Globex Digital - USA | India
Permanent Job
Bengaluru / Bangalore
,
India
4-20 years
gate-level
timing reports
EDT compression
debug skills
Memory BIST implementation
RTL-level
ATPG
constraint issues
Scan
Verification
DFT modes
Static Timing
4 months ago
SoC Verification Engineer
Truechip
Permanent Job
Bengaluru / Bangalore
,
India
3-8 years
Testbench
RTL
PCI Express
Assertion-based verification methodology
AMBA AHB/AXI
System C
MIPI
HVL
Usb
Soc
DDR
Ethernet
System Verilog
5 months ago
Frontend Technical Manager
hireinfinity consulting
Permanent Job
Bengaluru / Bangalore
,
India
8-16 years
Product Support for Pre-production
RTL Manipulation for DFT
Continuous Improvement
Documentation
RTL Coding Guidelines and Code Review
Project Planning and Execution
Stakeholder Communication
Clock Domain Crossing (CDC)
EDA Tools for Front End
Verification Planning and Management
Product Support for Post-production
Top Level Integration
Digital Verification
Rtl Design
Coding
3 months ago
Sr. ASIC Engr Verification/Design
Infinera
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
system level requirements
Signal Processing
Debug
RTL
ASIC
lab validation
Verification
filter performance
Dsp
Fpga
Matlab
Python
5 months ago
Frontend Technical Manager
Company Name Confidential
Permanent Job
Bengaluru / Bangalore
10-20 years
50000 - 10000000 INR
Chip Design
Rtl Design
RTL Coding
Verification
4 months ago
Software Engineer- Principal
Siemens EDA (Siemens Digital Industries Software)
Permanent Job
Noida
,
India
8-10 years
Low Power SOC Design
Dc
Fusion compiler
SV
RTL to GDS flow
Gate sign off tools
Prime Power
Verification
Prime time
Synthesis
ASIC
VHDL
Zebu
digital logic
RTL Architect
joules
Perl
Verilog
Python
Tcl
4 months ago
Lead Software Engineer
Siemens EDA (Siemens Digital Industries Software)
Permanent Job
Noida
,
India
2-6 years
Debugging Skills
Dc
Fusion compiler
RTL to GDS flow
low-power SOC design principles
Simulation
Gate sign off tools
Prime Power
Prime time
Design
Synthesis
ASIC
VHDL
digital logic
Place & Route
SV
Verification
Zebu
RTL Architect
joules
Verilog
Python
Hdl Languages
Perl
Tcl
4 months ago
Mgr Logic Design
Rambus
Permanent Job
Bengaluru / Bangalore
,
India
2-10 years
processes
Emulation
Methodologies
tape-outs
Ip
RTL
product concepts
ASIC
silicon design
Micro-architecture
Verification
Validation
Soc
Debugging
5 months ago
Physical Design Engineer
Sintegra Inc.
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
floor-planning
multi-power domain design
RTL
area (PPA)
Place & Route
LVS checks
advanced technology nodes
Attention To Detail
Physical Design Engineer
Power
Cadence Implementation tool suite
communication
Synthesis
Timing
EMIR/PV closure
physical verification (PV) and signoff
DRC
EMIR (Electromigration and IR drop) analysis and closure
problem-solving abilities
Teamwork Skills
low-power design techniques
GDSII
Python
Performance
Tcl
5 months ago
Front-end Technical Manager (Chip Design)
Ssquad Global
Permanent Job
Bengaluru / Bangalore
,
India
10-20 years
Synthesis
Dft
cdc
project management
EDA Tools
Stakeholder Management
Verification
power management
RTL coding guidelines
Digital Design
4 months ago
ASIC Physical Engineer Staff
Juniper Networks
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
Physical Synthesis
Physical Verification
RTL
Cadence
Mentor
Design closure
Place & Route
Design planning
ASIC
SI prevention
Physical Design
Gds
EDA Tools
Power reduction
Floor Planning
Timing Constraints
Synopsys
Unix
Static timing analysis
Perl
Tcl
4 months ago
Design Verification Engineer
Acumen
Permanent Job
Bengaluru / Bangalore
,
Hyderabad / Secunderabad, Telangana
4-8 years
SOC/IP Verification
System Verilog/UVM
RTL
5 months ago
Technologist, ASIC Development Engineering
Western Digital
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
Sta
Rtl Design
Dft
PPA
Optimization
floorplanning
Verification
Physical Design
Eda
3 months ago
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