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51
Rtl Jobs in Noida
Member of Consulting Staff
Siemens
Permanent Job
Noida
,
India
0-2 years
ASIC
Synthesis
Dc
RTL
SV
Fusion compiler
Verification
digital logic
Gate sign off tools
VHDL
Zebu
RTL Architect
Prime time
joules
Gds
Prime Power
Low Power SOC
Verilog
Tcl
Python
Perl
30 days ago
Lead Product Validation Engineer
Siemens
Permanent Job
Noida
,
India
7-12 years
ASIC
Synthesis
Dc
Simulation
SV
Fusion compiler
Place & Route
Verification
digital logic
Low Power SOC design principles
Gate sign off tools
VHDL
Zebu
RTL to GDS flow
RTL Architect
Prime time
joules
Prime Power
Verilog
Tcl
Python
Debugging
Perl
a month ago
Member of Consulting Staff
Siemens
Permanent Job
Noida
,
India
2-8 years
VHDL
UPF
RTL
systemverilog
parallel algorithms
Dft
C++
C
a month ago
STA Engineer
Digicomm Semiconductor
Permanent Job
Hyderabad / Secunderabad, Telangana
,
Bengaluru / Bangalore
,
Noida
,
Pune
,
India
5-7 years
Sta
methodology development
Timing Analysis
RTL
timing optimization
Physical Design
resistance effects
Dft
Timing Constraints
Timing Closure
Verification
timing margins
Clock Tree Synthesis
parasitic capacitance
a month ago
Physical Design Engineer
DesignNex Technologies
Permanent Job
Noida
,
India
1-3 years
ASIC
RTL
Eda
Fpga
Perl
Python
Tcl
a month ago
Lead Software Engineer
Cadence
Permanent Job
Noida
,
India
4-6 years
RTL
Sta
C++
Verilog
Eda
Linux
a month ago
Member of Consulting Staff
Siemens Technology
Permanent Job
Noida
,
India
2-8 years
VHDL
UPF
RTL
systemverilog
parallel algorithms
Dft
C++
C
a month ago
Pre - Silicon Validation
Zealogics.com
Permanent Job
Remote
,
India
8-12 years
CPU Verification
processor
Memory
analytical
validation content
Uvm
Graphics
Video
RTL validation
Design
system simulation models
architecture
validation platforms
staging
Audio
verification test plans
validation coverage
display
Ip
Problem Solving
test bench infrastructure
AMBA
Axi
feature scoping
Pre-Si validation
AHB
C
Ovm
Debugging
System Verilog
C++
Soc
Pci
5 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Delhi
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
4 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Noida
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
4 months ago
STA/Timing Sign-off Engineer - Sr Lead
Qualcomm Technologies, Inc
Permanent Job
Noida
,
India
1-6 years
PD Implementation
High frequency Datapath intensive Cores
Electronics Engineering
Power Estimation
Computer Science
Primetime/Tempus
Rtl Design
ASICs
Synthesis
Dft
Physical Synthesis
Power teams
multi voltage design convergence
Tcl/Perl scripting
Constraint development
Static Timing Analysis (STA)
Clock Tree Synthesis
hardware engineering
4 months ago
STA/Synthesis Engineer
7Rays Semiconductors India Private Limited
Permanent Job
Noida
,
India
3-5 years
Sta
Logical aware Synthesis
CTS
constraint development
RTL design team
Sub system level
Timing Closure
PRO Clock gating checks
Synthesis
Logical Equivalence check
DMSA flow
Prelayout timing analysis
UNIX env
Placement
final tapaout timing closure
HMs team
Block level
Post layout timing analysis
Manual ECO
PD team
Tcl Scripting
Chip Level
Static Timing Analysis
4 months ago
Physical Design Engineer
KeenHeads
Permanent Job
Noida
,
India
2-4 years
Circuit Design
team environment
Analytical Skills
written communication skills
Problem-solving
Physical Verification
Physical Design
EDA Tools
Verbal Communication Skills
Rtl Design
Logic Design
Scripting Languages
5 months ago
Software Engineer- Principal
Siemens EDA (Siemens Digital Industries Software)
Permanent Job
Noida
,
India
8-10 years
Low Power SOC Design
Dc
Fusion compiler
SV
RTL to GDS flow
Gate sign off tools
Prime Power
Verification
Prime time
Synthesis
ASIC
VHDL
Zebu
digital logic
RTL Architect
joules
Perl
Verilog
Python
Tcl
4 months ago
Technical Lead Verification Engineer
Incise Infotech Private Limited
Permanent Job
Noida
,
India
0-2 years
Verdi
constraint random tests
RTL/TB issues
Formal techniques
SV/UVM environments
GLS
Verilog
System Verilog
5 months ago
R&D Engineering, Architect
Synopsys Inc
Permanent Job
Noida
,
India
15-17 years
ASIC design flow
Advanced nodes
debug skills
EDA tool
design methodology
Optimization
r&d
Synthesis
Physical Synthesis
formal verification
Field-support
VLSI design methodologies
implementation products
RTL Coding
Communication Skills
Digital Design
Unix
Functional Specifications
Python
Tcl
5 months ago
Sr. Engineer
Synopsys Inc
Permanent Job
Noida
,
India
3-5 years
ASIC
RTL
Digital Design
PERL
Verilog
Python
Tcl
5 months ago
ASIC Digital Design Engr, II
Synopsys Inc
Permanent Job
Noida
,
India
3-5 years
LINT
cdc
ASIC
RDC
Debug
RTL
Digital Design
PERL
Verilog
Python
Tcl
5 months ago
R&D Engineer II
Synopsys Inc
Permanent Job
Noida
,
India
1-4 years
ASIC flows
Design for Test
Rtl Design
spyglass
VHDL
frontend digital design
EDA Tools
C/C++
perl
System Verilog
Verilog
Python
Tcl
5 months ago
Principal Engineer Physical Design Application Engineer
Synopsys Inc
Permanent Job
Noida
,
India
12-15 years
Physical Implementation
Multi Source CTS
Physical Synthesis
Synopsys implementation tools
RTL-GDS implementation methodologies
unix
perl
Machine Learning
Tcl
5 months ago
STA/Timing Engineer Staff/Sr Staff
Qualcomm Technologies, Inc
Permanent Job
Noida
,
India
2-4 years
STA timing analysis
Timing Constraints
monte carlo
process technology enablement
automation scripts
Layout Parasitic Extraction
CTS
PT/Tempus
Qualcomm Hexagon DSP IPs
Signal Integrity
Latch transparency handling
ASIC back-end design flows
device phy
digital flow design implementation RTL to GDS
AOCV/POCV concepts
feed through handling
multi-cycle path handling
Spice simulation Hspice/FineSim
Tcl
Perl
Awk
4 months ago
R&D Engineer II
Synopsys Inc
Permanent Job
Noida
,
India
1-4 years
Design for Test (DFT)
ASIC flows
Problem-solving
Rtl Design
software testing methodology
spyglass
VHDL
frontend digital design
EDA Tools
automation scripts
C/C++
testing scripts
perl
System Verilog
Verilog
Debugging
Python
Tcl
5 months ago
Engineer - DFT
Qualcomm Technologies, Inc
Permanent Job
Noida
,
India
2-4 years
simulating test vectors
Dft
Scan Insertion
ATPG
equivalence check
RTL lint tool
MBIST
Problem Solving Skills
Jtag
perl
Shell
4 months ago
Lead Software Engineer
Siemens EDA (Siemens Digital Industries Software)
Permanent Job
Noida
,
India
2-6 years
Debugging Skills
Dc
Fusion compiler
RTL to GDS flow
low-power SOC design principles
Simulation
Gate sign off tools
Prime Power
Prime time
Design
Synthesis
ASIC
VHDL
digital logic
Place & Route
SV
Verification
Zebu
RTL Architect
joules
Verilog
Python
Hdl Languages
Perl
Tcl
4 months ago
LMTS (IP Developer)
Siemens EDA (Siemens Digital Industries Software)
Permanent Job
Noida
,
India
5-11 years
Rtl Design
ASICs
VHDL
System C/C++
Micro-Architecture
High Level Synthesis
FPGAs
Verilog
Digital Signal Processing
4 months ago
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