Rtl Jobs in Delhi

Physical Design Engineer

Permanent Job

Noida ,

India

1-3 years

ASIC RTL Eda Fpga Perl Python Tcl

a month ago

Member of Consulting Staff

Permanent Job

Noida ,

India

2-8 years

VHDL UPF RTL systemverilog parallel algorithms Dft C++ C

a month ago

STA Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

Bengaluru / Bangalore ,

Noida ,

Pune ,

India

5-7 years

Sta methodology development Timing Analysis RTL timing optimization Physical Design resistance effects Dft Timing Constraints Timing Closure Verification timing margins Clock Tree Synthesis parasitic capacitance

a month ago

ASIC Physical Design, Staff Engineer

Permanent Job

Noida ,

India

5-7 years

Sta CTS Design Compiler Fusion Compiler RTL Synthesis formal verification Gds Placement IP Subsystem implementation IC Compiler/2 CAD automation methods physical implementation Floor-Planning synopsys tools industry tools IC design Formality Hercules/ICV Physical Verification FE flows Power Planning primetime Star-RCXT EMIR Signoff Python Routing Perl Tcl

a month ago

Lead Software Engineer

Permanent Job

Noida ,

India

4-6 years

RTL Sta C++ Verilog Eda Linux

a month ago

Pre - Silicon Validation

Permanent Job

Remote ,

India

8-12 years

CPU Verification processor Memory analytical validation content Uvm Graphics Video RTL validation Design system simulation models architecture validation platforms staging Audio verification test plans validation coverage display Ip Problem Solving test bench infrastructure AMBA Axi feature scoping Pre-Si validation AHB C Ovm Debugging System Verilog C++ Soc Pci

5 months ago

Software Engineer- Principal

Permanent Job

Noida ,

India

8-10 years

Low Power SOC Design Dc Fusion compiler SV RTL to GDS flow Gate sign off tools Prime Power Verification Prime time Synthesis ASIC VHDL Zebu digital logic RTL Architect joules Perl Verilog Python Tcl

5 months ago

LMTS (IP Developer)

Permanent Job

Noida ,

India

5-11 years

Rtl Design ASICs VHDL System C/C++ Micro-Architecture High Level Synthesis FPGAs Verilog Digital Signal Processing

4 months ago

Senior Member Technical Staff (C-Level Implementation)

Permanent Job

Noida ,

India

2-4 years

Power Planning CTS RTL Timing Analysis Gds Placement C C++ Routing Hdl Linux Python Tcl Systemc

3 months ago

Lead Software Engineer

Permanent Job

Noida ,

India

2-6 years

Debugging Skills Dc Fusion compiler RTL to GDS flow low-power SOC design principles Simulation Gate sign off tools Prime Power Prime time Design Synthesis ASIC VHDL digital logic Place & Route SV Verification Zebu RTL Architect joules Verilog Python Hdl Languages Perl Tcl

5 months ago

STA/Timing Sign-off Engineer - Sr Lead

Permanent Job

Noida ,

India

1-6 years

PD Implementation High frequency Datapath intensive Cores Electronics Engineering Power Estimation Computer Science Primetime/Tempus Rtl Design ASICs Synthesis Dft Physical Synthesis Power teams multi voltage design convergence Tcl/Perl scripting Constraint development Static Timing Analysis (STA) Clock Tree Synthesis hardware engineering

4 months ago

STA/Synthesis Engineer

Permanent Job

Noida ,

India

3-5 years

Sta Logical aware Synthesis CTS constraint development RTL design team Sub system level Timing Closure PRO Clock gating checks Synthesis Logical Equivalence check DMSA flow Prelayout timing analysis UNIX env Placement final tapaout timing closure HMs team Block level Post layout timing analysis Manual ECO PD team Tcl Scripting Chip Level Static Timing Analysis

4 months ago

Technical Lead Verification Engineer

Permanent Job

Noida ,

India

0-2 years

Verdi constraint random tests RTL/TB issues Formal techniques SV/UVM environments GLS Verilog System Verilog

5 months ago

R&D Engineering, Architect

Permanent Job

Noida ,

India

15-17 years

ASIC design flow Advanced nodes debug skills EDA tool design methodology Optimization r&d Synthesis Physical Synthesis formal verification Field-support VLSI design methodologies implementation products RTL Coding Communication Skills Digital Design Unix Functional Specifications Python Tcl

5 months ago

Sr. Engineer

Permanent Job

Noida ,

India

3-5 years

ASIC RTL Digital Design PERL Verilog Python Tcl

5 months ago

ASIC Digital Design Engr, II

Permanent Job

Noida ,

India

3-5 years

LINT cdc ASIC RDC Debug RTL Digital Design PERL Verilog Python Tcl

5 months ago

R&D Engineer II

Permanent Job

Noida ,

India

1-4 years

ASIC flows Design for Test Rtl Design spyglass VHDL frontend digital design EDA Tools C/C++ perl System Verilog Verilog Python Tcl

5 months ago

Principal Engineer Physical Design Application Engineer

Permanent Job

Noida ,

India

12-15 years

Physical Implementation Multi Source CTS Physical Synthesis Synopsys implementation tools RTL-GDS implementation methodologies unix perl Machine Learning Tcl

5 months ago

STA/Timing Engineer Staff/Sr Staff

Permanent Job

Noida ,

India

2-4 years

STA timing analysis Timing Constraints monte carlo process technology enablement automation scripts Layout Parasitic Extraction CTS PT/Tempus Qualcomm Hexagon DSP IPs Signal Integrity Latch transparency handling ASIC back-end design flows device phy digital flow design implementation RTL to GDS AOCV/POCV concepts feed through handling multi-cycle path handling Spice simulation Hspice/FineSim Tcl Perl Awk

4 months ago

R&D Engineer II

Permanent Job

Noida ,

India

1-4 years

Design for Test (DFT) ASIC flows Problem-solving Rtl Design software testing methodology spyglass VHDL frontend digital design EDA Tools automation scripts C/C++ testing scripts perl System Verilog Verilog Debugging Python Tcl

5 months ago

Engineer - DFT

Permanent Job

Noida ,

India

2-4 years

simulating test vectors Dft Scan Insertion ATPG equivalence check RTL lint tool MBIST Problem Solving Skills Jtag perl Shell

4 months ago

Applications Engineering, Staff Engineer

Permanent Job

Noida ,

India

2-3 years

Synthesis Design Compiler Logical Equivalence Check Fusion Compiler SERDES serial ata Gate Level simulation RTL PCI Express PrimeTrime Static Timing Analysis

5 months ago

Applications Engineering, Staff Engineer

Permanent Job

Delhi ,

India

2-3 years

Synthesis Design Compiler Logical Equivalence Check Fusion Compiler SERDES serial ata Gate Level simulation RTL PCI Express PrimeTrime Static Timing Analysis

5 months ago

Home

Job Category

Top Searches

Rtl Jobs in Delhi

Physical Design Engineer

Member of Consulting Staff

STA Engineer

ASIC Physical Design, Staff Engineer

Lead Software Engineer

Pre - Silicon Validation

Software Engineer- Principal

LMTS (IP Developer)

Senior Member Technical Staff (C-Level Implementation)

Lead Software Engineer

STA/Timing Sign-off Engineer - Sr Lead

STA/Synthesis Engineer

Technical Lead Verification Engineer

R&D Engineering, Architect

Sr. Engineer

ASIC Digital Design Engr, II

R&D Engineer II

Principal Engineer Physical Design Application Engineer

STA/Timing Engineer Staff/Sr Staff

R&D Engineer II

Engineer - DFT

Applications Engineering, Staff Engineer

Applications Engineering, Staff Engineer