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320
Rtl Jobs in Bengaluru Bangalore
Analog Mixed Signal Design Verification Engineer
Texas Instruments
Permanent Job
Bengaluru / Bangalore
,
India
2-5 years
Cadence Tools
checkers
spec
RTL
Cadence
Uvm
corner-cases
GLS
Problem-solving
randomization
assertions
ASI
Audio
communication
Digital
SV
coverage-feedbacks
stimulus
AMs
silicon
TB
Teamwork
Regression
audio signal processing
Eda
perl
Spi
Testplan
Verilog
Debugging
I2c
Dsp
python
Analog
Shell
6 days ago
Sr Staff Trace Design Engineer
MIPS
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
RTL
waveform debugging tools
logic design principles
Simulators
trace
Debug
micro-architecture
low-power architecture techniques
Scripting Language
Soc
Perl
Python
4 days ago
DFT Engineer
Intel
Permanent Job
Bengaluru / Bangalore
,
India
5-8 years
Dft
spyglass
TAP
ATPG
Ip
RTL
MBIST
post-silicon support
Manufacturing Engineering
Soc
4 days ago
DFT Engineering Lead
Intel
Permanent Job
Bengaluru / Bangalore
,
India
8-9 years
Dft
ATPG
TAP
Scan
RTL
MBIST
Soc
4 days ago
DFT Engineer
Intel
Permanent Job
Bengaluru / Bangalore
,
India
5-8 years
Dft
spyglass
TAP
ATPG
Ip
RTL
MBIST
post-silicon support
Manufacturing Engineering
Soc
4 days ago
Senior FV Engineering Manager
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
formal verification methodologies
DV
Synopsys VC Formal
industry-standard formal verification tools
Cadence JasperGold
Mentor Questa Formal
high-speed interconnect protocols
RTL
protocol compliance
Digital Design
SystemVerilog Assertions (SVA)
a day ago
Digital Designer
Infineon Technologies
Permanent Job
Bengaluru / Bangalore
,
India
8-9 years
DV verifications
Mentor
effort
AMS methodologies
regulators
DACs
switched cap circuits
Verilog-D
SV-RNM
Verilog-A
Mentoring Junior engineer
Digital
SV
project dynamics
Rtl Coding Styles
analog circuit basics
ADCs
optimization of simulation bench
MSV
Skill
charge pumps
Eldo ADMS
simulation time
Verilog-AMS
verification for IPs
Analog Design
multi-site development environment
Synopsys
Schedule
alternative verification plans
op-amps
Verilog Hdl
Cadence
project team
UVM testbench development
proposing new scenarios
analog and mixed signal building blocks
AMS simulation environment
Comparators
current mirrors
Real
xrun
mixed signal perspective
irun
Testcase Debug
AMS Verification
XA-VCS
product specifications
behavioral modeling
Scope
Scripting
Python
Test Plan Preparation
Analog
Perl
Tcl
4 days ago
Physical Design Lead / Manager
SiliconAuto India
Permanent Job
Bengaluru / Bangalore
,
India
15-17 years
Sta
Problem Solving
Signoff
power analysis
PPA
Signal Integrity Analysis
RTL
Cadence
Verification
Dft
ASIC
Physical Design
ISO 26262
Floor Planning
Mentor Graphics
Synopsys
Clock Tree Synthesis
Communication
GDSII
Routing
Soc
3 days ago
VLSI Engineer
Wipro
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
rtl verification
Uvm
HVL
Hdl
Ovm
System Verilog
4 days ago
Staff Engineer Design
Infineon Technologies
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Synthesis
FINFET technologies
Place & Route
Functional Safety
Timing Closure
RTL Coding
Technical Leadership
Scripting Languages
Programming Skills
5 days ago
Silicon AI/ML Architect, TPU, Google Cloud
Google
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
AI/ML
RTL
Emulation
Go
Physical Design
ASIC
Design
Packaging
Verification
area
Power
Cost
Performance
Soc
C++
Python
Silicon Validation
5 days ago
ASIC Digital Design Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
1650000 - 1574000 INR
ASIC design flow
Synthesis
bug resolution
Documentation
Timing Analysis
Verilog/System Verilog
Digital Design
semiconductor technology
Place And Route
Electronic Devices
silicon chips
Rtl Design
target application requirements
area efficiency
performance optimization
ASIC projects
ASIC solutions
power optimization
Test Plans
4 days ago
Staff Design Verification Engineer- CPU Subsystem
Tenstorrent
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
DFD IP
RTL
Uvm
C++
System Verilog
4 days ago
ASIC Design Engineer
7Rays Semiconductors India Private Limited
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
LINT
cdc
Vlsi
Ai
RTL
UCIe
UPF
Sd
BT
RDC
HBM
CXL
WiFi
Usb
Soc
DDR
Pcie
4 days ago
SOC Design Verification Engineer
7Rays Semiconductors India Private Limited
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
SV-OVM/SV-UVM Methodologies
video interfaces
AXI/AHB bus protocol
secure JTAG
PCI-e/USB/Ethernet/CPU
Perl/Python
ARM processor integration
RTL concepts
I2S/Audio
encryption/decryption[AES/SHA/RSA] IP integrations
I3C
System Verilog
5 days ago
Digital Design Engineer
Suitable AI
Permanent Job
Bengaluru / Bangalore
,
India
3-5 years
cdc
Simulation Tools
Digital Design
RTL micro architectures development
Electrical Engineering
Problem-solving
Presentation
VHDL
RDC
ASI/TDM
RTL Coding
communication
Synthesis
constraint development
Memory Architecture
digital timing analysis
Teamwork
LINT
audio signal chain
Fpga
Verilog
Debugging
I2c
System Verilog
Scripting
3 days ago
Statt Design Verification Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Verdi
RTL Design Verification
Verilog/System Verilog
Uvm
Coverage Collection
Integration Flows
Python/Perl/TCL
EDA Verification Tools
ASICs
spyglass
VHDL
Formal
VC-Formal
Simulation
Build/Release Flows
Test Planning
Debugging
Vcs
Soc
Ips
14 hours ago
Sr Staff Design Verification Methodology Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
Verdi
RTL
Uvm
systemverilog
spyglass
VHDL
VC-Formal
Eda
Vcs
Perl
Verilog
System Verilog
Python
Tcl
14 hours ago
Formal Verification, Sr Staff Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Unix/Linux Automation Shell
IEEE Math Libraries
Skill
Security Architecture
Floating Point Arithmetic Operations
Verification Signoff
Verification Methodology
Formal Verification Tool
Hardware Design
formal verification
Assertion-based Verification
Simulation
automotive safety
C/C++
Rtl Design
Scripting
Perl
Python
Tcl
14 hours ago
Staff Design Verification Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Verdi
RTL Design Verification
Verilog/System Verilog
Uvm
Coverage Collection
Integration Flows
Python/Perl/TCL
EDA Verification Tools
ASICs
spyglass
VHDL
Formal
VC-Formal
Simulation
Build/Release Flows
Test Planning
Debugging
Vcs
Soc
Ips
14 hours ago
Staff Design Verification Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Verdi
RTL Design Verification
Verilog/System Verilog
Uvm
Coverage Collection
Integration Flows
Python/Perl/TCL
EDA Verification Tools
ASICs
spyglass
VHDL
Formal
VC-Formal
Simulation
Build/Release Flows
Test Planning
Debugging
Vcs
Soc
Ips
14 hours ago
Principal Design Engineer
Arm
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
LINT
cdc
VHDL
ASIC
RDC
Design for Debug
RTL
Fpga
Verilog
Arm
3 days ago
Sr Design verification Engineer- Semiconductor Industry
DBSI Services
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
test bench development
Uvm
arm architecture
UPF
Secure boot
Rtl Design
ASIC
constrained random verification processes
C/C++
functional coverage
low power camera
Secure JTAG
code coverage
Scan Insertion
formal verification tools
Timing Analysis
CPU Security
Simulation Tools
test pattern generation
Regression
equivalence checking
Verilog
Python
Perl
Tcl
14 hours ago
Silicon Physical Design Engineer I
Google Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-4 years
Physical Design Methodology
Floor Planning
Synthesis
RTL
Area
Low-Power Design Methodologies
PnR Tools
Power
Flow Validation
Gds
Computer Architecture
Shell
Performance
Tcl
Python
Perl
3 days ago
Analog Mixed Signal Design Verification
Suitable AI
Permanent Job
Bengaluru / Bangalore
,
India
3-5 years
digital logic
audio signal processing
corner-cases
Presentation
coverage-feedbacks
Problem-solving
analog behavioral modelling
RTL
gls
cadence simulator
Teamwork
verilog a
wreal
randomization
Regression
stimulus
communication
sv/uvm
silicon debug
asi protocols
Eda
Testplan
Spi
perl
Debugging
I2c
Shell
python
2 days ago
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