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318
Rtl Jobs in Bengaluru Bangalore
ASIC Front-end Implementation Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-8 years
Design Compiler
RTL Synthesis
VC-SpyGlass
Fusion Compiler
Formality
RTL
Reset Domain Crossing
LEC
UPF
systemverilog
spyglass
Clock Domain Crossing
CPF
Prime Time
Perl
Verilog
Python
Tcl
5 months ago
FPGA Lead engineer
Megh Computing, Inc.
Permanent Job
Bengaluru / Bangalore
,
India
0-5 years
DDR4
Intel Quartus
ddr2
RTL
Xilinx Vivado
SignalTap
systemverilog
SDRAMs
Logic Analyzer
Axi
Avalon
Fpga
Ddr3
Linux
Verilog
Tcl
Ethernet
Python
Pcie
Shell Programming
Git
5 months ago
SoC Design Engg - SD
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
7-9 years
RTL
coverage analysis
product-level parameters
Place And Route
EDA Tools
power and noise analysis
placing
Synthesis
flow automation
power/clock distribution
multiple power domain analysis
Floor Planning
electrical rule checking
static and dynamic power integrity
Reliability
layout verification
formal equivalence verification
structural design checking
physical clock design
Gds
Timing Closure
Dft
Clock Tree Synthesis
Methodologies
static timing analysis
routing
5 months ago
Staff Engineer, Applications Engineering
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
Physical Implementation
methodology changes
RTL-GDS
debug skills
Synopsys implementation tools
Communication Skills
Scripting
5 months ago
DFT Engineer
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
7-9 years
SoC tools
IO DFx
BScan
ATPG/MBIST tools
multi-die package approach
analog DFT
Rtl Design
Design Compiler
Dft
Synthesis
spyglass
Tessent
ATPG
Scan
micro-architecture
MBIST
boundary scan
Tcl Scripting
Vcs
Jtag
Perl
Verilog
System Verilog
5 months ago
Camera IP Verification - Sr Lead Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-5 years
RTL design verification
GLS
Verification aptitude
Uvm
RTL debug skills
systemverilog
Coverage closure
dpi
camera verification
Firmware/emulation
Assertions based verification
BUS Protocols
Problem Solving Skills
Python
Perl
5 months ago
Formal Verification CAD Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-3 years
CHI
Cadence
Rtl Design
Axi
APB
EDA Tools
Synopsys
AHB
PERL
I2c
Python
System Verilog
Tcl
4 months ago
FPGA Principal Engineer
Thales
Permanent Job
Bengaluru / Bangalore
,
India
15-17 years
CVS
LVDS/Video
arinc 429
RTL
MILSTD 1553
Synthesis
RS-232
VHDL
RS-485/422
Subversion (SVN)
DO-254 Process assurance
Questasim
make
Formal Pro
HDL Designer
Quest CDC
P&R
Fpga
Shell Scripts
Pcie
Verilog
Python
Git
Perl
Ethernet
5 months ago
Emulation Engineer/Lead
Mirafra Technologies
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Netlist
RTL
trace files
log files
waveform viewers
Palladium
microcode trace dumps
Axi
Fpga
Debuggers
Spi
DDR
Shell
Pcie
Sata
I2c
Ruby
Python
System Verilog
Usb
C++
Perl
Pci
Tcl
5 months ago
SoC Design Engg - Emulation
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
6-10 years
pre-silicon validation
Timing Concepts
UCIe
Problem-solving
Rtl Design
SoC Architectures
high speed serial interfaces
Zebu emulation model
CXL
emulation domain
networking domain knowledge
caching/memories coherency
Perl
Pcie
intel architecture
Debugging
Scripting Languages
Python
5 months ago
R&D Engineering, Sr Staff Engineer
Synopsys
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
procs
Extraction
Spice
RTL
signoff
DV
PNR
Gds
ip development
Circuit Design
namespace
Algorithms
Verilog
Tcl
5 months ago
Senior Lead Engineer / Sr Engineer - Software Engineering
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
1-2 years
Distributed Processing
issue resolution
SW engineering
multiprocessing
Place And Route
technical innovations
Decision Support
computational problems
Tools
AI/ML
chip RTL
Technology
memory footprint
optimizing partitioning
Big Data Analytics
Fpga
Flows
Automation
cloud
continuous development
Gui
Data Analytics
5 months ago
R&D Engineering, Sr Staff Engineer
Synopsys
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
Formality
RTL
Physical Verification
spyglass
spice output
Gds
timing signoff methodologies
TCL programming
ip development
Vcs
Qa
Git
5 months ago
R&D Engineer II
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
1-4 years
ASIC flows
Design for Test
Rtl Design
spyglass
VHDL
frontend digital design
EDA Tools
C/C++
perl
System Verilog
Verilog
Python
Tcl
5 months ago
ASIC Digital Design Engr, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
UFS
cdc
Architecture
CHI
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
R&D Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-12 years
software specification
RTL Synthesis
analytical
Problem-solving
formal verification
design process
Compilers
synthesis techniques
Algorithms
C
C++
Regression Testing
UNIX
Linux
Debugging
data structures
5 months ago
ASIC Digital Design Engr, Sr I
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
UFS
Architecture
CHI
SpyGlass CDC/RDC
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
DC/Fusion Compiler
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
Staff Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
chip design flow
DRC convergence
CTS
Report Generation
analytical
physical design implementation
LVS
Dfm
Problem-solving
Timing Closure
PNR flows
Scripting skills
Placement
Antenna
synopsys tools
density checks
RTL synthesis
DRC
ICV
physical design database
Power
Debugging
Python
Perl
Tcl
5 months ago
Application Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
staff engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
8-10 years
Verilog/VHDL RTL level designs
gprof
timing constrains
FPGA prototyping
purify
C/C++ programming
EDA software
graph algorithms
static timing analysis
Digital Logic Design
Coverity
data structures
5 months ago
Senior/Staff/Sr Staff Physical Design Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
7-15 years
Physical Verification
RTL
Physical Implementation
GDSII
Unix
Perl
Tcl
5 months ago
LPASS DV Sr Lead Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
1-3 years
Verdi
RTL/TB
Vlsi
HDLs
SV/UVM
low power architecture
UPF
Perl
Verilog
System Verilog
Python
4 months ago
Design Engineer:
Delancey Technologies
Permanent Job
Bengaluru / Bangalore
,
India
2-5 years
Sta
Synthesis
Verilog compilers/simulators
front-end design
RTL design fundamentals
Dft
RTL synthesis
constraints development
linters
clock-domain crossing checkers
System-Verilog
Perl
Verilog
Scripting Languages
Python
Tcl
4 months ago
GPU SOC Validation Engineer
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
6-8 years
RTL Debugging
Emulation
Test Plan development
Simulation
Uvm
CPU/GPU architecture
Ovm
System Verilog
Programming Skills
5 months ago
SR Application Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
3-5 years
power analysis
Advanced Node
RTL
Physical Design
low power/multi-voltage physical implementation
CAD automation methods
floorplanning
Timing
ASIC implementation
DRC closure
DRC/LVS
Logic Synthesis
Placement
Parasitic Extraction
equivalence checking
GDSII
Design Methodologies
Clock Tree Synthesis
static timing analysis
routing
Python
data preparation
Perl
Tcl
5 months ago
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