Place Route Jobs

MTS Silicon Design Engineer

Permanent Job

India

7-9 years

RTL Synthesis IP integration Timing Analysis EM Dual Patterning Ir analytical establishing design methodology primetime circuit/logic simulation Placement DRC Design Compiler Power-plan LVS Cadence Genus computer organization tools for logic synthesis Layout Physical Verification CTS ICC2 clock and power gating techniques Synopsys Fusion Compiler Timing Closure Apache Redhawk FinFET Attention To Details scan stitching Place And Route floorplanning Schematics Problem Solving design optimization logic equivalence GDS2 architecture Extraction physical/timing/electrical quality Formal Equivalence final signoff Innovus PNR tools Mentor Graphics Calibre Crosstalk Analysis Floor-plan Physical Implementation Clock Tree Synthesis StarRC Routing

a month ago

PnR Implementation Staff Engineer

Permanent Job

Noida ,

India

2-9 years

CMOS technology Fusion compiler Physical Verification Place And Route physical design concepts CTS Innovus flooplanning STA analysis PnR Implementation Tcl Perl python

a month ago

Physical Design and Verification Engineer.

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Performance Optimization Documentation LVS power optimization Verification IR Drop Analysis ASICs Area Optimization Physical Design Timing Closure DRC Place And Route Clock Tree Synthesis

4 months ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

IC design Floor Planning RTL timing constraint design closure Timing Analysis Physical Verification Place And Route timing signoff ESD analysis timing ECO physical implementation Synthesis crosstalk analysis formal verification EM analysis low power verification netlist power grid implementation Clock Tree Synthesis power analysis

5 months ago

Backend Technical Manager

Permanent Job

Bengaluru / Bangalore ,

India

8-16 years

Product Support for Pre-production Packaging and Assembly Considerations Continuous Improvement Place and Route Optimization Tapeout Process Documentation Project Planning and Execution Physical Design and Optimization Stakeholder Communication Synthesis Timing Closure and Signal Integrity Clock Tree Synthesis (CTS) and Power Distribution Network (PDN) Dft Physical Verification Hierarchical Design and IP Integration formal verification EDA Tools for Back End Technology Node Migration Multi-Voltage Design Post-Silicon Debugging design for manufacturing Product Support for Post-production

3 months ago

IPPD - Physical design Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-4 years

CTS Electronics Engineering PD implementation Cadence Innovus Physical Implementation Physical Verification PDN Floor-planning clocking architecture power optimization Computer Science Timing Closure Low Power verification PPA critical cores STA concepts Place And Route Synopsys ICC2 formal verification Fpga Perl Scripting Python Dsp hardware engineering Tcl

4 months ago

Physical Design Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

Guntur ,

India

5-10 years

clock planning signal integrity analysis analog ip integration deepsub micron processes Physical Design variations analysis noise glitch tapeout Synthesis electrical rules process variation effects crosstalk delay modeling techniques primetime power plan Place And Route Dfm synopsys icc2 Physical Verification power / ir drop Floor Planning Timing Closure integrated package Parasitic Extraction DFY Clock Tree Synthesis perl Tcl

3 months ago

Senior Engineer ( RTL/FPGA System Design)

Permanent Job

Bengaluru / Bangalore ,

India

1-2 years

kernel debuggers Content Debug support SOC design Validation PCDDR ARM CPU Digital Circuits Uvm SoC architectures Synthesis LPDDR3/4 Waveform generation Place And Route Dsp Fpga Jtag System Verilog Python Tcl

3 months ago

Senior Engineer I - ASIC Design

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

floor-planning CTS IR/EM analysis Ip LEC LVS Place And Route Physical Design Dfm Physical Verification density checks Calibre pad-ring integration ASIC/ SoC Physical Design Cadence PnR/STA tools Timing Closure DRC scripting/automation skills FinFET node designs Antenna advanced process nodes

3 months ago

Backend Technical Manager - Semiconductor Chip Design

Permanent Job

Bengaluru / Bangalore

10-20 years

1000000 - 8000000 INR

Physical Design Synthesis Dft Place And Route power integrity project management EDA Tools Timing Closure Signal Integrity multi-voltage design stakeholder communication semiconductor chip design static timing analysis

5 months ago

Physical Design Engineers (RTL2GDSii Engineers)

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

RTL2GDSii Convergence formal verification Dc Synopsys Tool suite Calibre/ICV primetime Ansys Redhawk-SC Conformal/Formality Floor-planning Timing Analysis DRC/LVS VC-LP Design Flow Cadence Tool Suite IR/EM analysis Logic Synthesis Place And Route ICC2/Fusion/Innovus Tcl Python Perl

4 months ago

Physical Design Engineers (RTL2GDSii Engineers)

Permanent Job

Bengaluru / Bangalore ,

India

10-15 years

Dc IR/EM analysis Synopsys Tool suite Cadence Tool Suite DRC/LVS Convergence Ansys Redhawk-SC RTL2GDSii primetime Calibre/ICV Timing Analysis Conformal/Formality Logic Synthesis Floor-planning Place And Route ICC2/Fusion/Innovus Design Flow formal verification VC-LP Perl Python Tcl

4 months ago

Applications Engineering, Staff Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

4-6 years

Synthesis Synopsys implementation tools scripting (tcl / unix / perl) Physical Implementation Place And Route RTL-GDS

4 months ago

CPU - PD- MTS Silicon Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

design checks Memory Controller Timing Analysis circuit/logic simulation DPU Place And Route Physical Design Logic Synthesis Layout Schematics Cpu Gpu Perl Computer Architecture Python Tcl

5 months ago

Backend Technical Manager ( Semi Conductor Chip Design )

Permanent Job

Bengaluru / Bangalore

10-20 years

4000000 - 8000000 INR

Physical Design Dft Synthesis Place And Route power integrity Optimization Eda

4 months ago

ASIC Physical Design, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

physical implementation Sta Timing Pv Ir LVS Place And Route frontend design DRC perl Chip Level Tcl

5 months ago

Physical Design Engineers (RTL2GDSii Engineers)

Permanent Job

Bengaluru / Bangalore ,

India

5-7 years

5 months ago

MTS Silicon Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

design checks Memory Controller Timing Analysis circuit/logic simulation DPU Place And Route Physical Design Logic Synthesis Layout Schematics Cpu Gpu Perl Computer Architecture Python Tcl

5 months ago

Intern - VLSI DI

Permanent Job

Pune ,

India

0-2 years

Physical design implementation setup time Circuit Design Timing Concepts Analog Circuit Design Equivalence check EDA Tools Power CMOS fabrication process Frequency of circuit operations power dissipation ASIC design flow calculations of maximum load on circuit performance hold time requirements effect of transition Layout Design Timing Analysis Place And Route Shell Scripting Languages Logic Design Perl Tcl

5 months ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-6 years

Dc IR/EM analysis Synopsys Tool suite Cadence Tool Suite Convergence primetime Calibre/ICV Synthesis RTL2GDS Timing Analysis Conformal/Formality DRC/LVS clean-up VCLP Floor-planning Place And Route ICC2/Fusion/Innovus Design Flow formal verification Soc Scripting

5 months ago

Senior Structural Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

CTS MPCTS CTMESH RTL LVS Synthesis DRC Floorplan Clock Tree Synthesis GDSII Auto Place and Route Perl Python Tcl

5 months ago

ASIC Physical Design Engr, Sr

Permanent Job

Pune ,

India

5-7 years

analog/digital interfaces Design Compiler PERC primetime Fusion Compiler FinFET ICC2 RTL Digital Design LVS Calibre physical timing analysis tools architecture CAD automation methods timing signoff Synthesis physical verification tools Place And Route TSMC implementation flows Timing Constraints ERC DRC low-power design techniques ICV GDSII Python Perl Tcl

5 months ago

Applications Engineering, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-5 years

Verilog Hdl Verification English Synthesis MIPI Physical Design Parallel interfaces ASIC Design Analog Design Simulation Place And Route Design Reuse High-speed SERDES

5 months ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

5-10 years

Dc IR/EM analysis Synopsys Tool suite Cadence Tool Suite DRC/LVS Convergence primetime Calibre/ICV Synthesis RTL2GDS Timing Analysis Conformal/Formality VCLP Floor-planning Place And Route ICC2/Fusion/Innovus Design Flow formal verification Scripting

5 months ago

SoC Design Engg - SD

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

RTL coverage analysis product-level parameters Place And Route EDA Tools power and noise analysis placing Synthesis flow automation power/clock distribution multiple power domain analysis Floor Planning electrical rule checking static and dynamic power integrity Reliability layout verification formal equivalence verification structural design checking physical clock design Gds Timing Closure Dft Clock Tree Synthesis Methodologies static timing analysis routing

5 months ago

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Place Route Jobs

MTS Silicon Design Engineer

PnR Implementation Staff Engineer

Physical Design and Verification Engineer.

Physical Design Engineer

Backend Technical Manager

IPPD - Physical design Staff Engineer

Physical Design Engineer

Senior Engineer ( RTL/FPGA System Design)

Senior Engineer I - ASIC Design

Backend Technical Manager - Semiconductor Chip Design

Physical Design Engineers (RTL2GDSii Engineers)

Physical Design Engineers (RTL2GDSii Engineers)

Applications Engineering, Staff Engineer

CPU - PD- MTS Silicon Design Engineer

Backend Technical Manager ( Semi Conductor Chip Design )

ASIC Physical Design, Staff Engineer

Physical Design Engineers (RTL2GDSii Engineers)

MTS Silicon Design Engineer

Intern - VLSI DI

Physical Design Engineer

Senior Structural Design Engineer

ASIC Physical Design Engr, Sr

Applications Engineering, Staff Engineer

Physical Design Engineer

SoC Design Engg - SD