Fresher Place Route Jobs

Applications Engineering, Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Place & Route Sta Synthesis Equivalency check RTL Coding Macro & Standard Cell Placement Clock Tree Synthesis Advanced Timing Optimization Constraints Routing

5 months ago

Physical Design Methodology Engineer

Permanent Job

Bengaluru / Bangalore ,

India

Fresher

550000 - 550000 INR

Sta Synthesis CTS analytical Full-chip Floor-planning ICC2 Physical Verification ICC Place And Route standard place and route flows Customer Support RTL2GDSII layout closure timing convergence Innovus automation skills design implementation Fusion Compiler Primetime Timing Closure Block-level Problem Solving PERL Tcl

5 days ago

ASIC Digital Design, Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

0-2 years

1650000 - 1574000 INR

ASIC design flow Synthesis bug resolution Documentation Timing Analysis Verilog/System Verilog Digital Design semiconductor technology Place And Route Electronic Devices silicon chips Rtl Design target application requirements area efficiency performance optimization ASIC projects ASIC solutions power optimization Test Plans

a day ago

Physicial Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Floor Planning standard cell designs auto place and route algorithms RC de lay electromigration custom polygon editing data path register files selfheating electrically robust layout schematic layout verification rc extraction

6 days ago

ASIC Digital Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

1650000 - 1574000 INR

4 days ago

Physical Design and Verification Engineer.

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

Performance Optimization Documentation LVS power optimization Verification IR Drop Analysis ASICs Area Optimization Physical Design Timing Closure DRC Place And Route Clock Tree Synthesis

4 months ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

0-2 years

IC design Floor Planning RTL timing constraint design closure Timing Analysis Physical Verification Place And Route timing signoff ESD analysis timing ECO physical implementation Synthesis crosstalk analysis formal verification EM analysis low power verification netlist power grid implementation Clock Tree Synthesis power analysis

5 months ago

Intern - VLSI DI

Permanent Job

Pune ,

India

0-2 years

Physical design implementation setup time Circuit Design Timing Concepts Analog Circuit Design Equivalence check EDA Tools Power CMOS fabrication process Frequency of circuit operations power dissipation ASIC design flow calculations of maximum load on circuit performance hold time requirements effect of transition Layout Design Timing Analysis Place And Route Shell Scripting Languages Logic Design Perl Tcl

5 months ago

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Fresher Place Route Jobs

Applications Engineering, Engineer

Physical Design Methodology Engineer

ASIC Digital Design, Engineer

Physicial Design Engineer

ASIC Digital Design Engineer

Physical Design and Verification Engineer.

Physical Design Engineer

Intern - VLSI DI