Equivalence Checking Jobs

Sr Design verification Engineer- Semiconductor Industry

Permanent Job

Bengaluru / Bangalore ,

India

5-10 years

test bench development Uvm arm architecture UPF Secure boot Rtl Design ASIC constrained random verification processes C/C++ functional coverage low power camera Secure JTAG code coverage Scan Insertion formal verification tools Timing Analysis CPU Security Simulation Tools test pattern generation Regression equivalence checking Verilog Python Perl Tcl

15 hours ago

R&D Software Engineer - LLM, Generative AI

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

Formal Technologies digital logic C/C++ Equivalence Checking Algorithms Eda Cloud Technologies Containers data structures Python Kubernetes Tcl

10 days ago

Synthesis Engineer

Permanent Job

Noida ,

India

1-2 years

Synthesis LP signoff tools LEC Fusion Compiler VHDL QoR optimization Genus Regression Equivalence Checking Python Configuration Management Version Control Tcl Verilog

a month ago

Senior Staff, CAD Engineer (RTL-to-GDS implementation flow)

Permanent Job

Bengaluru / Bangalore ,

India

15-17 years

Synthesis Design Compiler Fusion Compiler Implementation IC Compiler II formal equivalence checking P&R Physical Design Perl Python Tcl

5 months ago

Applications Engineering, Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

2-3 years

power analysis Sta Extracti on Design Compiler Advanced Node ICC2 Quantus RTL Tempus IRdrop analysis Conformal Physical Design Voltus Front end Synthesis tools Innovus RTL Coding Genus CAD automation methods FusionCompiler Synthesis ASIC implementation Formality DRC/LVS Verification primetime formal checking Back-end P&R tools Star-RCXT redhawk Parasitic Extraction equivalence checking GDSII Design Methodologies static timing analysis Scripting Python Perl Tcl

5 months ago

R&D Engineering, Staff Engineer

Permanent Job

Noida ,

India

2-4 years

digital logic configuration management tools C/C++ Equivalence Checking Formal Technologies Algorithms Eda software development process data structures Debugging Tools

5 months ago

SoC/IP Pre-Silicon Verification Engineer

Permanent Job

Bengaluru / Bangalore ,

India

7-12 years

Low Power Verification Uvm UPF RTL make Logic Equivalence Checking assertion based verification System Verilog Python Perl

5 months ago

SR Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

power analysis Advanced Node RTL Physical Design low power/multi-voltage physical implementation CAD automation methods floorplanning Timing ASIC implementation DRC closure DRC/LVS Logic Synthesis Placement Parasitic Extraction equivalence checking GDSII Design Methodologies Clock Tree Synthesis static timing analysis routing Python data preparation Perl Tcl

5 months ago

Senior Engineer, Applications Engineering

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

2-3 years

5 months ago

Senior Applications Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

technical problem-solving Synthesis Repair embedded memories AE deductive Simulation Verbal Communication RTL personal responsibility memory test Dft ASIC Written Communication logic libraries IO libraries self-motivation equivalence checking static timing analysis Soc Verilog Scripting Languages

5 months ago

&D Engineering, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

10-12 years

digital logic configuration management tools C/C++ Equivalence Checking Formal Technologies Algorithms Software Development Eda data structures Debugging Tools

5 months ago

R&D Engineering, Sr Engineer

Permanent Job

Noida ,

India

2-4 years

digital logic configuration management tools C/C++ Equivalence Checking Formal Technologies Algorithms Eda software development process data structures Debugging Tools

5 months ago

SR Application Engineer

Permanent Job

Bengaluru / Bangalore ,

India

3-5 years

5 months ago

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

Physical Design equivalence checks CTS strategies performance optimization primetime Scan boundary scan power integrity Jtag protocols timing ECO implementation RTL TestMax ATPG STA setup automation scripts static timing verification System Verilog Logic Equivalency checking BIST architectures die size optimization Timing Closure Dft memory BIST Tessent tool sets TetraMax Tcl Python PERL Shell

12 days ago

SoC Design Engg - SD

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

RTL coverage analysis product-level parameters Place And Route EDA Tools power and noise analysis placing Synthesis flow automation power/clock distribution multiple power domain analysis Floor Planning electrical rule checking static and dynamic power integrity Reliability layout verification formal equivalence verification structural design checking physical clock design Gds Timing Closure Dft Clock Tree Synthesis Methodologies static timing analysis routing

5 months ago

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Equivalence Checking Jobs

Sr Design verification Engineer- Semiconductor Industry

R&D Software Engineer - LLM, Generative AI

Synthesis Engineer

Senior Staff, CAD Engineer (RTL-to-GDS implementation flow)

Applications Engineering, Engineer

R&D Engineering, Staff Engineer

SoC/IP Pre-Silicon Verification Engineer

SR Application Engineer

Senior Engineer, Applications Engineering

Senior Applications Engineer

&D Engineering, Staff Engineer

R&D Engineering, Sr Engineer

SR Application Engineer

DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years

SoC Design Engg - SD