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219
Ddr Jobs
ASIC Digital Design Engr, Sr I
Synopsys Inc
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
0-2 years
UFS
cdc
Architecture
CHI
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
ASIC Digital Design Engr, Sr II
Synopsys Inc
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
0-2 years
DFA
Semiconductor
UFS
FMEDA
Safety Concept analysis
5 & 11
Functional Safety
UCIe
Fault injection
design understanding
ISO26262 Part 4
automotive applications
Dfmea
DDR
Front End Design
Pcie
Ethernet
5 months ago
ASIC Digital Design, Engineer
Synopsys Inc
Permanent Job
Pune
,
India
1-2 years
LINT
cdc
AMBA
Synthesis
MIPI-UFS
Unipro
SD-MMC
Formal checking
Perforce
Usb
DDR
Shell
Pcie
Perl
Verilog
Ethernet
System Verilog
5 months ago
A&MS Layout Design Engr, Sr I
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
LPE
DDR/HBM IP
layout automation
top level verification flow
Dfm
written communication skills
CMOS
28nm
bondpad layout
Scripting skills
Esd
Verification
latchup layout design considerations
IO frame
mitigation
Place & Route
IR considerations
Analog Mixed-signal layout
digital flow
IO abutment rules
Strategies
process technology
LEF generation
ASIC physical design flow
EM
DRC/LVS
pitch requirements
power rail routings
Advanced floorplanning techniques
high-speed digital
Deep submicron effects
Advanced tool usage
Verbal Communication Skills
FinFET layouts
5 months ago
Lead Verification Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
7-8 years
MTI
Uvm
Sd
Unipro
VC Formal
UFS
i2s
eMMC
AMBA
Axi
MIPI
NC
VMM
I3C
vip
Vcs
Ovm
Spi
DDR
Pcie
Verilog
I2c
System Verilog
Python
Usb
Uart
Perl
Ethernet
Tcl
5 months ago
ASIC Digital Design, Sr Staff Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
6-7 years
DFA
FMEDA
VDC-M Codecs
RTL
VESA DSC
AMBA
ISO 26262
Dfmea
DDR
Pcie
Perl
Ethernet
Python
Tcl
5 months ago
ASIC Digital Design Engr, Sr I
Synopsys Inc
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
0-2 years
UFS
CHI
Uvm
AMBA
Axi
SOC RTL designs
BFMs
APB
IP cores
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
Digital PDTE - Sr Lead Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
1-3 years
Semiconductor manufacturing process
High-Speed IO
C#
LabVIEW
C
Python
DDR
4 months ago
ASIC Digital Design Manager
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
10-15 years
Testbench
DDR/LPDDR5
Uvm
Perl
Verilog
System Verilog
Python
5 months ago
Layout Design, Sr Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
LPE
DDR/HBM IP
layout automation
top level verification flow
Dfm
written communication skills
CMOS
28nm
bondpad layout
Scripting skills
Esd
Verification
latchup layout design considerations
IO frame
mitigation
Place & Route
IR considerations
Analog Mixed-signal layout
digital flow
IO abutment rules
Strategies
process technology
LEF generation
ASIC physical design flow
EM
DRC/LVS
pitch requirements
power rail routings
Advanced floorplanning techniques
high-speed digital
Deep submicron effects
Advanced tool usage
Verbal Communication Skills
FinFET layouts
5 months ago
SoC/Interface IP Applications Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Organizational
project management
SOC design
IC design
Sales Support
semiconductor ip
MIPI
ASIC
SERDES
connectivity protocols
program management
Verification
customer facing
Eda
Usb
technical communication
Interface
DDR
Pcie
Ethernet
5 months ago
Design Verification Engineer II
Cadence Design Systems
Permanent Job
Bengaluru / Bangalore
,
India
2-4 years
SV/UVM
HBM
Design Verification
IP Verification
Functional Verification
Memory IP
GDDR
DDR
System Verilog
5 months ago
Layout Design Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-10 years
Analog Mixed-signal layout
IO abutment rules
IR considerations
top level verification flow
Place & Route
EM
DDR IOs
customers
CMOS
power rail routings
bondpad layout
DRC/LVS
coordination activities
mitigation
Process
Verification
development teams
floorplanning techniques
ASIC physical design flow
FinFET layouts
Dfm
Remote site interaction
written communication skills
Digital
IO frame
layout automation
LPE
Deep submicron effects
LEF generation
Esd
Scripting skills
pitch requirements
Verbal Communication Skills
Technical Leadership
5 months ago
ASIC Digital Design, Staff Engineer
Synopsys
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
CRV
technical review
test bench architecture
Problem Solving
eMMC
AMBA
Sd
MIPI
Dsc
Quality Improvement
Verification
Usb
Test Plans
Test Cases
DDR
Pcie
Ethernet
Debugging
5 months ago
Embedded Linux / BSP Engineer
Comminent
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
hardware schematics
test equipment
DDR RAM
porting board support packages
Rtc
C
C++
Iic
Uart
Device Driver
Spi
Yocto
Bootloader
Ethernet
Flash
Python
Linux Kernel
4 months ago
Emulation Engineer/Lead
Mirafra Technologies
Permanent Job
Bengaluru / Bangalore
,
India
5-7 years
Netlist
RTL
trace files
log files
waveform viewers
Palladium
microcode trace dumps
Axi
Fpga
Debuggers
Spi
DDR
Shell
Pcie
Sata
I2c
Ruby
Python
System Verilog
Usb
C++
Perl
Pci
Tcl
5 months ago
System Performance - Staff Engineer
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
Mobile UX Performance
Driver
mobile operating systems
HW
compiler construction
Android Game Performance
compiler
Operating System
SW
Ai
ARM based platforms
performance profiling tools
BUS Protocols
graphics programming
Chip Power Performance
Memory interface
Power
Noc
C
Cpu
Soc
Programming
Gpu
Windows
DDR
Javascript
Linux Os
Python
Java
Noc
C++
Multimedia
Android
Uefi
Storage
Shell
Linux
modem
5 months ago
A&MS Layout Design Engr
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
LPE
DDR/HBM IP
layout automation
top level verification flow
Dfm
written communication skills
CMOS
28nm
bondpad layout
Scripting skills
Esd
Verification
latchup layout design considerations
IO frame
mitigation
Place & Route
IR considerations
Analog Mixed-signal layout
digital flow
IO abutment rules
Strategies
process technology
LEF generation
ASIC physical design flow
EM
DRC/LVS
pitch requirements
power rail routings
Advanced floorplanning techniques
high-speed digital
Deep submicron effects
Advanced tool usage
Verbal Communication Skills
FinFET layouts
5 months ago
ASIC Digitial Design Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
Dc
cdc
CHI
Fusion Compiler
Uvm
spyglass
Synthesis
RDC
BFMs
Low Power Architecture
UFS
SV
Formality
AMBA
Axi
APB
Hdl
DDR
Pcie
System Verilog
Python
Usb
Perl
Ethernet
Tcl
5 months ago
MIPI ASIC Digital Design Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
3-7 years
MTI
Uvm
Sd
Unipro
AMBA2
UFS
eMMC
AMBA
Axi
NC
VMM
MIPI-I3C
vip
Vcs
Ovm
DDR
Pcie
Verilog
System Verilog
Python
Usb
Perl
Ethernet
Tcl
5 months ago
ASIC Digital Design Engr, II
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
LPDDR
Uvm
DDR
Shell
Perl
Verilog
System Verilog
Python
5 months ago
ASIC Digital Design Engr, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
0-2 years
UFS
cdc
Architecture
CHI
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
Principal Design Verification Engineer
Cadence Design Systems
Permanent Job
Bengaluru / Bangalore
,
India
6-8 years
SV/UVM
HBM
Design Verification
IP Verification
Functional Verification
Memory IP
GDDR
DDR
System Verilog
5 months ago
Sr ASIC Digital Design Engr
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-15 years
Uvm
eMMC
AMBA
Sd
MIPI
Oops
Perforce
Usb
Ovm
DDR
Shell
Pcie
Perl
Ethernet
System Verilog
5 months ago
ASIC Digital Design Engr, Sr I
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
UFS
Architecture
CHI
SpyGlass CDC/RDC
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
DC/Fusion Compiler
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
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