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Fresher compiler design jobs
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68
Compiler Design Jobs
ASIC Physical Design Engr, Sr
Synopsys Inc
Permanent Job
Pune
,
India
5-7 years
analog/digital interfaces
Design Compiler
PERC
primetime
Fusion Compiler
FinFET
ICC2
RTL
Digital Design
LVS
Calibre
physical
timing analysis tools
architecture
CAD automation methods
timing signoff
Synthesis
physical verification tools
Place And Route
TSMC
implementation flows
Timing Constraints
ERC
DRC
low-power design techniques
ICV
GDSII
Python
Perl
Tcl
5 months ago
EDA tools software engineer
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
2-3 years
Circuit
Projects
Simulation
Tools
Software
Intel
Design
Innovus
Design
StarRC
architecture
Vendors
backend
compiler
Digital
Hspice
chip
Languages
Custom
Development
Methodologies
CAD
ICC
Schematic
Spectre
Infrastructure
Layout
primetime
engineer
Environment
Fusion
Process
Eda
Flows
programming
Scripting
Groups
Analog
Shell
Linux
5 months ago
ASIC Physical Design, Sr Engineer
Synopsys Inc
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
3-5 years
Design Compiler
Dfm
ICC/ICC2/FC
formal verification
clock tree optimization
Dft
low-power design
CAD automation methods
physical implementation
synopsys tools
Extraction
Physical Synthesis
IC design
CAD
high speed clock design and distribution
floorplanning
Physical Compiler
Primetime SI
Hercules/ICV
Physical Verification
Signal Integrity
Hspice
Timing Constraints
Star-RCXT
Timing Closure
high-speed design
routing
Python
Perl
Tcl
5 months ago
Senior Engineer, Applications Engineering
Synopsys Inc
Permanent Job
Hyderabad / Secunderabad, Telangana
,
India
2-3 years
power analysis
Sta
Extracti on
Design Compiler
Advanced Node
ICC2
Quantus
RTL
Tempus
IRdrop analysis
Conformal
Physical Design
Voltus
Front end Synthesis tools
Innovus
RTL Coding
Genus
CAD automation methods
FusionCompiler
Synthesis
ASIC implementation
Formality
DRC/LVS
Verification
primetime
formal checking
Back-end P&R tools
Star-RCXT
redhawk
Parasitic Extraction
equivalence checking
GDSII
Design Methodologies
static timing analysis
Scripting
Python
Perl
Tcl
5 months ago
ASIC Front-end Implementation Engineer, Staff
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-8 years
Design Compiler
RTL Synthesis
VC-SpyGlass
Fusion Compiler
Formality
RTL
Reset Domain Crossing
LEC
UPF
systemverilog
spyglass
Clock Domain Crossing
CPF
Prime Time
Perl
Verilog
Python
Tcl
5 months ago
DFT Engineer
Intel Corporation
Permanent Job
Bengaluru / Bangalore
,
India
7-9 years
SoC tools
IO DFx
BScan
ATPG/MBIST tools
multi-die package approach
analog DFT
Rtl Design
Design Compiler
Dft
Synthesis
spyglass
Tessent
ATPG
Scan
micro-architecture
MBIST
boundary scan
Tcl Scripting
Vcs
Jtag
Perl
Verilog
System Verilog
5 months ago
Graphics Performance Modelling Architect
Qualcomm Technologies, Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-4 years
Memory
GPU power modeling
projection
PrimeTime PX
Power Artist
Design Verification
compiler development
characterizations
Post-Silicon
clock power
GPU driver
ASIC Design
Verification
power optimizations
GPU workload analysis
low-power ASIC design techniques
Assembly
Cuda development
CPU/GPU architecture/microarchitecture design development
industry tools
workload
low-power ASIC optimization
Vulkan
Vlsi Design
power verifications
systemverilog
tests
DirectX3D
Profiling
Pre-silicon
Estimation
Graphics architecture
register
Microarchitecture
Logic
GPU architecture
C/C++ Programming Language
Scripting
Verilog
Python
Performance
Correlation
Perl
Opengl
Opencl
4 months ago
ASIC Physical Design, Staff Engineer
Synopsys Inc
Permanent Job
Pune
,
India
5-7 years
analog/digital interfaces
Design Compiler
PERC
primetime
Fusion Compiler
FinFET
ICC2
RTL
Digital Design
LVS
Calibre
physical
timing analysis tools
architecture
CAD automation methods
timing signoff
Synthesis
physical verification tools
Place And Route
TSMC
implementation flows
Timing Constraints
ERC
DRC
low-power design techniques
ICV
GDSII
Python
Perl
Tcl
5 months ago
Senior Application Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
4-6 years
Design Compiler
primetime
Fusion Compiler
SERDES
PCI Express
5 months ago
ASIC Digital Design Engr, Sr I
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
5-10 years
UFS
Architecture
CHI
SpyGlass CDC/RDC
Formality
SOC design
Implementation
AMBA
Axi
Synthesis
APB
DC/Fusion Compiler
Simulation
Low Power Architecture
Rtl Design
Usb
DDR
Pcie
Perl
Ethernet
System Verilog
Python
Tcl
5 months ago
Application Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
ASIC Physical Design Engr, Sr
Synopsys Inc
Permanent Job
Pune
,
India
5-7 years
analog/digital interfaces
Design Compiler
PERC
primetime
Fusion Compiler
FinFET
ICC2
RTL
Digital Design
LVS
Calibre
physical
timing analysis tools
architecture
CAD automation methods
timing signoff
Synthesis
physical verification tools
Place And Route
TSMC
implementation flows
Timing Constraints
ERC
DRC
low-power design techniques
ICV
GDSII
Python
Perl
Tcl
5 months ago
Senior Software Developer-Automotive
thyssenkrupp India Pvt Ltd
Permanent Job
India
5-8 years
configuration and version management tools
embedded C software
AUTOSAR stacks
static code analysis
Embedded concepts
modelling tools
automotive protocols
Autosar
embedded compiler
requirement management tools
software and application design
Unit Testing
Operating Systems
Debugging Tools
Uml
5 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Pune
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
ASIC Physical Design, Manager
Synopsys Inc
Permanent Job
Noida
,
India
10-12 years
Sta
ICC/ICC2/Fusion Compiler
synopsys tools
ICV LVS
CAD automation method
Design Compiler
IR/EM
floorplanning
Physical Verification
Primetime SI
Synthesis
PNR
Star-RCXT
ERC
DRC
Pg
Industry EDA tools
Perl
Scripting
Python
Tcl
4 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Bengaluru / Bangalore
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
4 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
Applications Engineering, Staff Engineer
Synopsys Inc
Permanent Job
Delhi
,
India
2-3 years
Synthesis
Design Compiler
Logical Equivalence Check
Fusion Compiler
SERDES
serial ata
Gate Level simulation
RTL
PCI Express
PrimeTrime
Static Timing Analysis
5 months ago
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