Asic Physical Design Jobs

Layout Design, Sr Engineer

Permanent Job

Delhi ,

Hyderabad / Secunderabad, Telangana ,

Bengaluru / Bangalore ,

India

0-2 years

deep submicron effects asic physical design flow analog mixed-signal layout scripting skills cmos layouts Verbal Communication Skills written communication skills

5 months ago

Physical Verification engineer

Permanent Job

Bengaluru / Bangalore ,

India

7-9 years

Asic Physical Design EDA Tools Linux shell scripts custom circuit design Physical Verification Perl Python Tcl

5 months ago

A&MS Layout Design Engr, Sr I

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

LPE DDR/HBM IP layout automation top level verification flow Dfm written communication skills CMOS 28nm bondpad layout Scripting skills Esd Verification latchup layout design considerations IO frame mitigation Place & Route IR considerations Analog Mixed-signal layout digital flow IO abutment rules Strategies process technology LEF generation ASIC physical design flow EM DRC/LVS pitch requirements power rail routings Advanced floorplanning techniques high-speed digital Deep submicron effects Advanced tool usage Verbal Communication Skills FinFET layouts

5 months ago

Layout Design, Sr Engineer

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

5 months ago

Layout Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-10 years

Analog Mixed-signal layout IO abutment rules IR considerations top level verification flow Place & Route EM DDR IOs customers CMOS power rail routings bondpad layout DRC/LVS coordination activities mitigation Process Verification development teams floorplanning techniques ASIC physical design flow FinFET layouts Dfm Remote site interaction written communication skills Digital IO frame layout automation LPE Deep submicron effects LEF generation Esd Scripting skills pitch requirements Verbal Communication Skills Technical Leadership

5 months ago

Senior Design Engineer - Physical Design

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

Extraction PPA high-speed interfaces floorplanning Asic Physical Design Cadence Full chip Physical Design Signal Integrity clock distribution solutions IR Drop Analysis primetime Design Timing Primetime-SI ASIC fundamentals P&R Synopsys problem-solving skills PERL Static Timing Analysis Scripting Languages Tcl

4 months ago

Layout Design, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

Bengaluru / Bangalore ,

Noida ,

India

0-2 years

deep submicron effects asic physical design flow analog mixed-signal layout scripting skills cmos layouts Verbal Communication Skills written communication skills

5 months ago

A&MS Layout Design Engr

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

5 months ago

Senior Design Engineer- Physical Design

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

5-7 years

Cadence or Synopsys tools Asic Physical Design Full chip Physical Design Cadence Innovus ASIC fundamentals problem-solving skills 5nm node PERL Static Timing Analysis Tcl

4 months ago

Layout Design, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

LPE layout automation top level verification flow Dfm written communication skills CMOS latchup layout design high-speed digital layout bondpad layout Scripting skills Esd IO frame Place & Route IR considerations digital flow IO abutment rules process technology LEF generation ASIC physical design flow EM DRC/LVS layout co-ordination activities pitch requirements Analog Mixed-signal DDR/HBM IP layout power rail routings Remote site interaction Advanced floorplanning techniques Deep submicron effects Advanced tool usage Verbal Communication Skills FinFET layouts Technical Leadership

4 months ago

Layout Design, Staff Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-6 years

LPE DDR/HBM IP floorplanning techniques Dfm written communication skills CMOS 28nm bondpad layout Esd Verification latchup layout design considerations IO frame mitigation Place & Route IR considerations internal development teams Analog Mixed-signal layout customer implementation IO abutment rules process technology LEF generation ASIC physical design flow EM DDR/HBM PHY DRC/LVS pitch requirements power rail routings interactions with customers high-speed digital Deep submicron effects top-level verification flow Verbal Communication Skills FinFET layouts

4 months ago

Layout Design, Sr Engineer

Permanent Job

Bengaluru / Bangalore ,

India

2-6 years

LPE DDR/HBM IP floorplanning techniques Dfm written communication skills CMOS latchup layout design 28nm bondpad layout Esd Verification IO frame mitigation Place & Route IR considerations Analog Mixed-signal layout customer implementation IO abutment rules process technology LEF generation ASIC physical design flow EM DDR/HBM PHY DRC/LVS pitch requirements power rail routings high-speed digital Deep submicron effects top-level verification flow Verbal Communication Skills FinFET layouts

4 months ago

Principal Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

power optimization techniques floorplanning Multiple Projects fast-paced process nodes Signal Integrity Leadership Skills EDA Tools Timing Closure design teams Placement dynamic environment Physical Design Implementation problem-solving skills communication Clock Tree Synthesis routing Static Timing Analysis

a month ago

Senior Technologist, ASIC Development Engineering - Physical Design Lead (Full Chip)

Permanent Job

Bengaluru / Bangalore ,

India

12-14 years

power analysis Reliability timing optimization LVS Physical Design Dfm packaging interface Problem-solving bump thermal management packaging technologies communication advanced process nodes full-chip RDL bump patterns Methodologies die-to-package interconnects Timing Analysis physical design tools Floor Planning Signal Integrity Teamwork ERC DRC Placement RDL layouts manufacturability routing

a month ago

Staff Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

5-10 years

Sta Design Compiler RTL Conformal UPF DFT Compiler low power design Dft ASIC RTL Compiler Clp Shell PERL Tcl

a month ago

Staff Engineer, ASIC Development Engineering (Physical Design)

Permanent Job

Bengaluru / Bangalore ,

India

5-10 years

Sta Design Compiler RTL Conformal UPF DFT Compiler low power design Dft ASIC RTL Compiler Clp Shell PERL Tcl

a month ago

Physical Design Lead / Manager

Permanent Job

Bengaluru / Bangalore ,

India

15-17 years

Sta Problem Solving Signoff power analysis PPA Signal Integrity Analysis RTL Cadence Verification Dft ASIC Physical Design ISO 26262 Floor Planning Mentor Graphics Synopsys Clock Tree Synthesis Communication GDSII Routing Soc

3 days ago

Silicon AI/ML Architect, TPU, Google Cloud

Permanent Job

Bengaluru / Bangalore ,

India

8-10 years

AI/ML RTL Emulation Go Physical Design ASIC Design Packaging Verification area Power Cost Performance Soc C++ Python Silicon Validation

5 days ago

Physical Design Engineer

Permanent Job

Bengaluru / Bangalore ,

India

1-2 years

1864999 - 1593000 INR

CTS Tempus Floorplan Cadence Genus Voltus Problem-solving Innovus Physical Verification Eco Physical Design Collaboration ASIC chips Placement communication routing

6 days ago

ASIC Engineer

Permanent Job

Bengaluru / Bangalore ,

India

6-8 years

global signal planning Cadence LEC Mentor Calibre physical convergence Cadence Innovus Timing Closure Synopsys Formality multi Vt strategies ASIC Floor Planning I/O planning Design for Yield and Manufacturability Hierarchical design implementation approach Apache Redhawk Clock and Power distribution Power Integrity Analysis hard IP integration Primetime-DMSA RTL2GDS Physical Design Synopsys DC/DCG Synopsys ICV Synopsys ICC2 Python Perl Tcl

11 days ago

DESIGN VERIFICATION ENGINEERS (4+ years of Exp Only)

Permanent Job

Bengaluru / Bangalore ,

India

4-6 years

Uvm Verification STA-Synthesis Physical Design ASIC flow debugging skill AXI-AMBA protocol variants C/C++ Rtl Design tapeout services Integration System Verilog Makefile Shell Perl

7 days ago

Applications Engineering, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

1-3 years

ASIC design flow Physical Design Flow CMOS concepts Synopsys Digital Circuits

9 days ago

Director of Physical Design

Permanent Job

Bengaluru / Bangalore ,

India

5-15 years

ASIC EDA Vendors RTL chip development Physical Design Electrical Engineering GDSII communication technology

11 days ago

Applications Engineering, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

1-3 years

ASIC design flow Physical Design Flow CMOS concepts Synopsys Digital Circuits

9 days ago

Applications Engineering, Sr Engineer

Permanent Job

Hyderabad / Secunderabad, Telangana ,

India

1-3 years

ASIC design flow Physical Design Flow CMOS concepts Synopsys Digital Circuits

9 days ago

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Asic Physical Design Jobs

Layout Design, Sr Engineer

Physical Verification engineer

A&MS Layout Design Engr, Sr I

Layout Design, Sr Engineer

Layout Design Engineer

Senior Design Engineer - Physical Design

Layout Design, Sr Engineer

A&MS Layout Design Engr

Senior Design Engineer- Physical Design

Layout Design, Staff Engineer

Layout Design, Staff Engineer

Layout Design, Sr Engineer

Principal Engineer, ASIC Development Engineering (Physical Design)

Senior Technologist, ASIC Development Engineering - Physical Design Lead (Full Chip)

Staff Engineer, ASIC Development Engineering (Physical Design)

Staff Engineer, ASIC Development Engineering (Physical Design)

Physical Design Lead / Manager

Silicon AI/ML Architect, TPU, Google Cloud

Physical Design Engineer

ASIC Engineer

DESIGN VERIFICATION ENGINEERS (4+ years of Exp Only)

Applications Engineering, Sr Engineer

Director of Physical Design

Applications Engineering, Sr Engineer

Applications Engineering, Sr Engineer