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Synopsys Inc

Test & Validation Engineering, Engineer

Synopsys Inc
Early Applicant
  • 21 days ago
  • Be among the first 50 applicants
Exp: 1-2 Years
Bengaluru / Bangalore, India
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Job Description

  • Must have BSEE and 2+yrs exp or MSEE with :1 yrs experience
  • Work on projects or processes within area of responsibility in defined components
  • Productive professional who applies practical knowledge of organization policies & procedures to resolve variety of issues within functional area.
  • Sound fundamentals in Digital electronics. HDL Languages coding experience preferably in Verilog/VHDL/System Verilog
  • Understanding & experience in Formal concepts: FPV (Formal Property Verification), Coverage, Simulation, writing SVA
  • Has familiarity with scripting languages & developed some automation in previous projects preferably in: Python/Perl
  • Writing testplans/testcases/Run benchmark designs to validate complex tool features in Formal methodology
  • Reviewing, resolving and maintenance of daily regressions & benchmark failures
  • Diagnosis, troubleshooting, Automation testing of EDA tools internally

More Info

Industry:Other

Job Type:Permanent Job

Skills Required

VHDL
EDA Tools
Digital Electronics
Simulation
SVA
Hdl Languages
Perl
Verilog
System Verilog
Python

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Date Posted: 07/11/2024

Job ID: 99528251

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Synopsys Inc
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