This position is with STA signoff team part of The Custom Compute & Storage (CCS) group at Marvell, Bangalore. This team as part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for strong technical leaders having Full-Chip Static Timing Analysis experience on hierarchical designs using industry standard tools.
What You Can Expect
- As a STA engineer you will be part of our signoff team responsible for signing off timing for the next generation Multi-Ghz high-performance processor SOC and custom ASIC chips in leading-edge CMOS process technology.
- Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the global timing flow and making sure all the blocks meet timing requirements.
- Be responsible for .constraint development, validation at the block/subsystem/full chip level.
- Responsible for timing closure of sub systems/full chip across timing modes.
- Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
- Writing scripts in TCL and Perl to achieve productivity enhancements through automation.
What We're Looking For
- B-Tech/M-Tech candidate with 7+ years of hands-on experience and leadership in full-chip STA/Synthesis. Should have played a Timing lead role with 3+ years experience in handling Timing sign off for multi-million hierarchical designs.
- Should have hands on constraints development experience including third party IPs, budgeting , STA modes understanding (FUNC/TEST) and driving the timing closure for block, Subsystem as well as chip level.
- Driving the timing closure for block, Subsystem as well as chip level.
- Candidate should have excellent problem solving skills in timing domain, should be well versed with scripting language PERL/TCL/AWK/Shell .
- Candidate Should have experience in working with global teams as a timing lead, handling Customer/Stakeholder interactions, driving technical deliverables/dependencies across the design cycle (DFT/PD/FE/Power)
- Candidate should possess excellent inter-personal skills with experience in providing mentorship to junior engineers, reviewing designs and providing technical guidance
