Sensesemi is looking for high-quality, driven semiconductor engineers, interested in working in start-ups, and building products from the ground up!
We are developing a line of low-power AIoT SoC products to bring AI to the node at the edge. Our SoCs are highly integrated, ultra-portable, low-power IoT controllers, with AI inference on-die, RF connectivity, and a host of digital and analog interfaces for sensor inputs and communication. We also provide a full firmware stack that allows the development and deployment of AI/ML applications quickly and easily. Continuous and constant innovation, and a customer-first mindset are the cornerstones of our company.
We're looking for an RTL design engineer to implement complex peripheral design, MCU/NPU subsystem design, and fullchip integration. This role will involve a rich blend of tasks, challenges and learnings. One of your core duties will be to collaborate intensively with other designers and 3rd party IP providers to ensure that we are creating high quality, cutting-edge PPA designs.
Responsibilities
The employee is responsible for the RTL design and implementation of Sensesemi's AIoT products. The employee is expected to take complete ownership of multiple complex design challenges, which would include:
- Design of complex peripherals and subsystems
- Fullchip integration of subsystems
- Bring in best practices of design
- Run Lint and CDC checks on the RTL
- FPGA porting of designs
- Adding hooks in the design for design for debug (DFD)
- Work with verification and STA engineers to fix bugs and improve timing
- Debug & support for ATE testing
Qualifications
- Preferred BS/MS in EE, CS or related field
- 5-7+ years experience in RTL design or similar VLSI role
- Experience with microarchitecture development and writing RTL for modules from scratch
- Strong knowledge of Verilog and System Verilog
- Good understand of verification environments and test creation
- Strong understanding of various interface protocols like SPI, I2C, UART, etc.
- Good understanding of STA and timing constraints
- Good understanding of synthesis and logical equivalence
- Good skills in programming languages like Perl, Python, TCL, and/or Shell Scripting
- Very good communication skills
- Ability to work independently when needed
- Ability to break down complex, sometimes open-ended tasks into an actionable plan, and then implementing it
- Excellent problem-solving and analytical skills
- Experience with RISC-V or ARM designs and integration is a big plus
- Experience with neural network architecture and design is a plus
