Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements.
What You Can Expect
Very good knowledge on SCAN/ATPG/JTAG/MBIST
Good Knowledge and understanding on JTAG for IEEE1149.1/6 standards
Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)
Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques
Proven experience in Scan insertion techniques at block level and Chip top level
Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level
Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team
Good knowledge on Perl/ Tcl scripting
Proven experience on gate level simulations with notiming and SDF based simulations
Experience with Post-Si ramp up and debug on ATE
Should be able to independantly own and delivery tasks that are assigned
Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization
High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project
What Were Looking For
- bachelors degree in Computer Science, Electrical Engineering or related fields and 4-6 years of related professional experience. masters degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience.
