Job Description
Blaize leads new-generation computing unleashing the potential of AI to enable leaps in the value technology delivers to improve the way we all work and live. Blaize offers transformative edge computing solutions for AI data collection and processing at the edge of network, with a focus on smart vision applications including automobility, retail, security, industrial, and metro. Blaize has secured US$224M in equity funding to date from strategic and venture investors Franklin Templeton, DENSO, Daimler, SPARX Group, Magna, Samsung Catalyst Fund, Temasek, GGV Capital, Wavemaker, and SGInnovate. With headquarters in El Dorado Hills (CA), Blaize has teams in Campbell (CA), Cary (NC), and subsidiaries in Hyderabad (India), Abu Dhabi, and Leeds and Kings Langley (UK), with 250+ employees worldwide. www.blaize.com
Overview
Blaize is a groundbreaking deep technology company focused on making AI broadly accessible to enterprises and people. Our breakthrough silicon architecture and innovative software platform empower designers to exploit the benefits of AI and lead the largest tech transformation in decades more fully.
Description
We work on complex high performance, fully programmable, low power design of Graph Streaming Processor, an architecture specially designed for machine learning/visual applications. As a member of our focused group of HW engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both SDK and backend teams for performance tuning, area, and power optimizations of multi million gate design.
Education And Experience
BE/BTech/ME/MTech in Computer Science or Electronics or Electrical
8+ years of experience
Required Knowledge, Skills, And Abilities
Capability to understand a given block specification and come up with Micro Architecture
Capability to derive an architecture and micro architecture based on a given algorithm
Experience in processor design RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design.
Knowledge in digital logic for HW safety/protection ECC, Parity, WDT etc.
Experience of multi-million gate ASIC design and verification methodologies
Good understanding of Computer Architecture, ISA, Caches and Memory Hierarchy.
Experience in performance and power analysis of processor based systems.
Experience in AMBA AXI, AHB, and APB protocols
Knowledge of digital design methodologies and tool flow
Excellent logic design, debugging and problem-solving skills.
Experience in logic design with Verilog and/or System Verilog and validation/verification
Experience in lint checks, area optimization, power optimization, GLS, synthesis and timing analysis
Experience in Multi-clock domain, Interconnects
Knowledge on Memory subsystem
Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus.
Experience with DSP, Datapath design and floating-point math a plus
Understanding of GPU/AI/ML Processor architecture
Blaize is an equal opportunity employer. We pride ourselves on having a diverse workforce and we do not discriminate against any employee or applicant because of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law. We respect the gender, gender identity and gender expression of our applicants and employees, and we honor requests for preferred pronouns. It is our policy to comply with all applicable national, state and local laws pertaining to nondiscrimination and equal opportunity
