STA Engineer /IR EM Engineer / Physical verification Engineer

Cientra is hiring for multiple positions for like;

• STA Engineer with expertise of Constraints, Timing ECO, Sign off
• IREM Engineer with expertise of block and full chip level
• PDV (physical Verification) Engineer with expertise of block and full chip level

STA Engineer:-

*Key Responsibilities:

- Develop and maintain *STA constraints* to ensure accurate timing analysis.

- Perform *timing analysis* using industry-standard tools like *PrimeTime* or *Tempus*.

- Understand and apply *QTM* and *ETM* models for accurate timing prediction.

- Work with design teams to identify and resolve timing issues, and implement *timing ECOs* effectively.

- Collaborate with cross-functional teams to ensure quality and performance standards are met.

- Provide guidance on *DMSA* (Design Margin Static Analysis) to optimize designs for power, performance, and area.

- Drive the sign-off timing convergence for high-performance designs, setting up the STA infrastructure and sign-off convergence flows.

IREM Engineer:-

Key Responsibilities:

- Develop and refine the flow, scripts, and methodologies for various electrical analyses at both block and top levels.

- Perform static and dynamic *IR analysis, power and signal **EM analysis*, in-rush current/power-up analysis, and ESD checks.

- Collaborate with package and power integrity teams to optimize the overall power delivery network (PDN) performance.

- Implement power grids using industry-standard PnR tools (preferably ICC2 and/or Fusion Compiler).

- Validate the PG (power grid) using grid resistance and secondary PG resistance checks.

- Drive block and top-level electrical verification closure.

PDV (physical Verification) Engineer :-

Key Responsibilities:

- Develop and maintain *block-level physical verification flows* for DRC, LVS, and other checks.

- Perform *layout vs. schematic (LVS)* and *design rule checking (DRC)* using industry-standard tools (e.g., Calibre, IC Validator).

- Collaborate with layout designers to resolve physical design issues.

- Analyze and debug DRC violations, LVS mismatches, and other physical verification issues.

- Work closely with the design and layout teams to ensure compliance with process technology rules.

- Optimize layout for manufacturability and yield improvement.

- Participate in reviews of layout and physical verification results.

- Document physical verification procedures and best practices.

Qualifications:*

- Bachelor's or master's degree in electrical engineering or related field.

- 5 to 10 years of experience in top-level physical verification of large SoCs.

- Strong communication and teamwork skills.