Job Responsibilities
Your Key Responsibilities Would Include:
ASIC team is responsible for providing in house ASIC/FPGA solutions that are at the core of the Infinera Networking Solutions.
As a design member of the ASIC team, you will be:
- Identify DSP design requirements working with System/ASIC architecture team
- Model specific DSP related functions (for e.g clock recovery)
- Propose solutions and get them reviewed with senior architects
- Be responsible for implementing the architecture by taking it through planning, definition and implementation phase
- Do RTL coding and RTL checks
- Work with verification and lab validation teams to verify and test the implementation.
Job Requirements
- Candidate must have a Bachelor's Degree or higher in CS or EE with very good academics. Masters degree preferred.
- Signal processing knowledge (fundamentals and good understanding of terminologies used, should be able to participate in discussions around filter performance and system level requirements and debug)
- 4+ years experience
- Experience with Python or Matlab for DSP modelling
- Ability to communicate using diagrams and written documents
- Ability and desire to learn and work in a team
Education & Experience Necessary For Success
- Candidate must have a Bachelor's Degree or higher in CS or EE with very good academics. Masters degree preferred.
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment. 
