Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 2 years of experience with low power RTL and physical design optimization techniques.
- Experience with scripting languages (e.g., Python, Perl).
Preferred qualifications:
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture.
- Experience with RTL level power estimation/analysis tools.
- Ability to work separately and as part of a team.
- Excellent problem-solving and investigative skills.
- Excellent communication and teamwork skills.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level(RTL) and Netlist level.
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation.
- Drive power estimation and what if analysis for IP(s) and SubSystem(s) and drive closure of projections vs aimed gaps.
- Analyze power estimation reports to identify power saving opportunities and influence both the physical design aspect and the U-arch design aspects of the design for power reduction.
- Work with the Power Modeling team to analyze the power impact of different IP/SS states w.r.t battery life.
