Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with IP design for clocking, interconnects, and peripherals.
4 years of experience in people management, developing employees.
Experience with RTL design using Verilog/System Verilog and microarchitecture, ARM-based SoCs, interconnects, and ASIC methodology.
Preferred qualifications:
Master's degree in Electrical Engineering or Computer Engineering.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience leading IP/SoC design team for low power SoCs.
Ability to drive a multi-generational roadmap for IP/SoC development.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of the team that designs chassis IPs (NoC, Clock, Debug, QoS, etc.) and subsystems for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality RTL design. You'll solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance, power and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
Responsibilities
Lead a team that delivers fabric interconnect IP, platforms, and subsystems.
Drive multi-generation roadmap for design optimization.
Define micro-architecture details (e.g., interface protocol, block diagram, data flow, pipelines, etc.).
Oversee RTL development, debug functional, and performance simulations.
Participate in synthesis, timing/power estimation, and Field-Programmable Gate Array/silicon bring-up.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
