Alternate Job Titles:
- ASIC Physical Design Engineer
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using ASIC design flow (Gate2GDSII). You thrive in dynamic environments and have a knack for problem-solving and innovation. Your expertise in digital block implementation, from gate netlist to GDSII, is complemented by your hands-on experience with state-of-the-art ASIC flows. You understand the intricacies of design initialization, power planning, floor planning/macro placement, scan-chain reordering, CTS, route, and chip finishing steps.
You have a solid foundation in physical implementation, signoff verifications (DRC, LVS, Antenna), and reliability verifications (EMIR, ESD). Your ownership of writing MCMM and UPF for block designs showcases your leadership and technical prowess. You are adept at providing handoff data to other signoff closure like STA, formality, layout, and reliability verification.
With a minimum of 5 years of relevant experience in the physical design domain and a B.E/B.Tech/M.Tech in ECE/EE, you are ready to take on new challenges and contribute to groundbreaking projects.
What You'll Be Doing:
- Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows.
- Performing physical implementation of blocks from gate netlist to GDSII.
- Conducting signoff verifications, including layout verifications (DRC, LVS, Antenna) and reliability verifications (EMIR, ESD).
- Writing MCMM and UPF for block designs.
- Providing handoff data for other signoff closure processes like STA, formality, layout, and reliability verification.
- Collaborating with cross-functional teams to ensure the successful integration and testing of physical designs.
The Impact You Will Have:
- Enhancing the quality and reliability of our digital block implementations.
- Driving innovation in physical design methodologies and processes.
- Enabling the successful deployment of high-performance silicon chips.
- Contributing to the development of cutting-edge technology that powers next-generation applications.
- Supporting the continuous improvement of our ASIC design flow and tools.
- Ensuring the seamless integration of physical designs into larger systems and platforms.
What You'll Need:
- In-depth understanding of the ASIC physical design flow steps from gate netlist.
- Experience in testchip implementation and testing exposure is a plus.
- Exposure to Synopsys toolset (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable.
- Experience with FinFET designs is desirable.
- Experience in working on IO integration with wire-bond or flip-chip design is a big plus.
Who You Are:
- A problem solver with strong analytical skills.
- Detail-oriented with a focus on quality and reliability.
- Effective communicator and collaborator.
- Innovative thinker with a passion for technology.
- Self-motivated and able to work independently.
The Team You'll Be A Part Of:
Join a dynamic team of experts focused on pushing the boundaries of physical design and implementation. Our team is dedicated to continuous innovation and excellence, working collaboratively to solve complex challenges and deliver cutting-edge solutions. You'll be part of a supportive and inclusive environment where your contributions are valued and your professional growth is nurtured.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
