Our vision is to transform how the world uses information to enrich life for .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
JR64637 Senior/Staff Engineer, Design Enablement
Responsibilities include but are not limited to the following:
Do you want to be a part of an inclusive team
- Drive vertical integration with a network of collaborators varying from Business Units, Pathfinding, Design, Process, Integration, Reliability, Product Engineering, Probe, Test, Assembly, Mask Tech.
- Coordinate the work of engineers from process integration teams to provide Design rules and Device definitions to support die and scribe design
- Consolidate device test structure requirements as per project breakthroughs of technology node development and with various teams to achieve defined metrics and timelines
- Coordinate the pre-silicon build and post-silicon evaluation of device test structures which provide data for next generation devices and quantify process margin on current devices
- Partner with CAD teams to ensure complete coverage and high quality PDK work such as DRC/LVS/PEX decks, PCELLS, support spice models and design tools
- Pro-actively identify and address process issues and process window vs. die size issues stemming from specific database layout or layout techniques
- Ensure that the right DRC's (Design Rule Checks) are in place and take appropriate reaction to deviation from established design rules
- Drive effective multi-functional communication on issue resolution, and support Design Rule alignment across technology nodes
- Create layouts to qualify Design rules using industry standard layout automation tools
- Write custom rule decks to qualify Design rule definitions
Minimum Qualifications:
- BS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related field
- Senior level (5+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Device Characterization, Spice/Compact Modeling, PDK development
- Prior experience in enabling and/or Qualifying PDK components such as DRC/LVS/PEX decks, Spice models
- Ability to write scripts in Perl, Python, SKILL or SVRF
- Validated grasp and exposure to design & layout with the ability to do minor layout work with Pcells is desired
- Experience with transistor level circuit and layout design with sound understanding of underlying device physics
- Possess a deep understanding of the semiconductor process flow
- Validated understanding of mixed signal circuits such Multiplexers, Amplifiers, Drivers, and Charge pumps
- Exposure and familiarity with CAD group interactions, data post-processing, and the process of transferring DGS data all the way to mask generation
- Think and communicate clearly in urgent and stressful situations
