About the job
As a digital design engineer, you will be part of a team with a charter to develop new TI SerDes products (FPD-Link) using state-of-the-art process technology, that solve our customers challenges primarily in the automotive space. You and the team will drive modeling, design, and implementation of integrated circuits with a focus on high-speed SerDes solutions.
You will interface with various engineering teams within the product line including analog design, layout, validation, test, systems, applications and marketing to successfully execute new products from concept to volume production and subsequent support.
You will be a core member in a design team driving flawless execution, while finding innovative solutions to customers problems through out of the box thinking to deliver highly differentiated products.
What will you be doing in this role (Responsibilities)
- Be a key team member from product definition till release to market, working closely with all functions (e.g. systems, analog design, verification, test, applications).
- Define or enhance the micro-architecture for digital blocks/top and designing them along with rest of the team.
- RTL development and verification (RTL and Gate level).
- Collaborate with analog designers on mixed-signal and DSP blocks and interfaces.
- Work closely with verification team to build the full-chip verification plan, tests. Support functional debugs and RCAs.
- Support silicon validation activities, test program development and the customer engagement and silicon/application debug needs.
- Drive architectural optimization for area, power and performance improvements for a given node.
- Address performance bottlenecks through micro-architecture.
What do we expect from you (Mini Qualifications)
- Hands on front-end design experience of complex multi clock domain blocks.
- Ability to convert high level system requirements/changes into micro-architectural changes and then into RTL
- Ability to extract the functionality / micro-architecture of existing design even with sparse legacy documentation
- Familiarity with verification environments to be able to actively participate in functional debugs
- Good knowledge on static timing analysis and constraints debugging.
- Understand and own in detail the functional specifications of the IPs/SoC
- Ensure that design-for-test (DFT) standards are addressed by design
- Participate in and conduct design reviews. Create the necessary design documentation
- Ability to take initiatives and drive the results working with team members across time-zones
- Handling & owning design deliverables and schedule
- Bachelors / Masters in Electrical / Electronics Engineering
Preferred Skills/ Experience
- 3-10 years of relevant experience
- Excellent RTL design (Verilog) skill including Lint, Simulation, Debug, Synthesis and LEC (preferably Cadence toolchain).
- Experience in identifying and implementing complex ECO in netlist.
- Experience in writing and debugging timing constraints at IP / SoC level
- Experience in silicon functional debug/RCA to map bugs to RTL. Familiarity with Si-bringup & Bench testing
- Experience in FPGA prototyping of full/parts of system would be a plus.
- Experience in digital signal processing and Matlab modeling would be a plus.
- Understanding of high-speed protocol and interfaces like CSI, DSI, MiPi, HDMI, Display Port etc
- Knowledge of PLL, SerDes, Encoders, Decoders, Video Compression, Video Encryption, I2C and SPI
