Senior Manager, ASIC Development Engineering - Physical Desing

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nJob Summary:

nWe are seeking a highly skilled and experienced Physical Design Lead with expertise in full-chip Redistribution Layer (RDL), bump, and packaging interface. The ideal candidate will lead the physical design efforts of our advanced semiconductor products, ensuring optimal performance, manufacturability, and reliability. This role involves close collaboration with cross-functional teams, including design, manufacturing, and packaging engineers.

nKey Responsibilities:

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  nDrive the full-chip physical design process, including floor planning, placement, routing, and timing optimization. Ensure design meets performance, power, area, and manufacturability requirements. Manage and guide a team of physical design engineers, providing technical direction and mentorship.

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  nDevelop and optimize full-chip RDL and bump layouts. Collaborate with packaging and manufacturing teams to define bump patterns and RDL structures. Ensure robust design solutions that meet electrical and mechanical constraints.

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  nWork closely with packaging engineers to ensure seamless integration between chip design and package. Define and optimize die-to-package interconnects, including considerations for signal integrity and thermal management. Address challenges related to package constraints and contribute to innovative packaging solutions.

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  nInterface with RTL designers, DFT engineers, and verification teams to ensure design consistency and compliance with project specifications. Collaborate with process engineers to understand and integrate process variations and constraints. Participate in design reviews and provide critical feedback to improve overall design quality.

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  nConduct thorough design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC). Perform timing analysis, power analysis, and signal integrity checks to validate design robustness. Ensure design meets all tape-out criteria and coordinate with foundry partners for successful fabrication.

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  nStay updated with the latest advancements in physical design tools, methodologies, and technologies. Implement best practices and drive continuous improvement in design processes and methodologies. Contribute to the development of in-house tools and scripts to enhance design efficiency and quality.

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  nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 12+ years of experience in physical design, with a focus on full-chip RDL, bump, and packaging interface.
• Proven track record of leading physical design projects from concept to tape-out.
• Strong knowledge of physical design tools and methodologies (e.g., Cadence, Synopsys etc).
• Expertise in floor planning, placement, routing, timing analysis, and DFM.
• Familiarity with packaging technologies and die-to-package interconnects.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.
• Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.

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