Senior Engineer II - Layout Design

• Lead layout design activity and work closely with design team.
• Produce high quality IPs/AMS Blocks/Macros.
• Drive Area estimation, floor planning, placement, routing, power planning, verification, EMIR , ESD-LUP verification and tape out activity.
• Mentor Junior Analog IC Layout engineers.
• Develop scripts.
• You will be reporting to Director -Layout Design

What youll need:

• Minimum 6+ years of experience in Analog Layout.
• Minimum Education requirement is bachelors degree in electrical engineering.
• Understanding of low parasitic, high frequency design techniques.
• Excellent understanding of analog layout concepts and issues.
• Experience in handling blocks and macros layout towards successful, high-quality, and timely execution
• Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry.
• Experience with multiple foundries in lower node eg: Samsung, TSMC, GF.
• Experience with Cadence tools (Virtuoso), Synopsys (CC), Calibre and ICV verification tools like LVS, DRC, Extraction etc.
• Experience with EMIR, PERC tools.
• Skill/TCL scripting experience.