Senior Design Verification Engineer

UVM, System Verilog, System C , Perl, Python , C/C++

Protocol Knowledge - APB/AXI/CHI

PCIE/CXL/UCIE/Ethernet

DDR5/LPDDR5/

JTAG/I3C/SPI

HBM

Arch Domain Knowledge - Processor, memory architecture, Coherency, Performance

Tools/Flows - Questa, Visualizer

Execute test plan and close coverage

Write C tests

Write SV Directed/constrained random tests

Write Cover points, coverage closure

Write SV Assertions

Develop UVM, SV testbench components, complex checker, high level stimulus

Strong debug and communication skills Experience: 7-10years

IP level verification

PCIE/CXL/UCIE/Ethernet/DDR SubSystem Verification

Processor verification

Virtualization

Coherent/non-coherent Fabric verification

SOC verification

Phy bring up

UPF simulation

Protocol Compliance Suite testing

Gate Level Simulation