Job Title: R&D Engineering, Staff Engineer
Job Location: Bangalore
Alternate Job Titles:
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a seasoned professional with a deep understanding of the complete characterization flows, library validation, and timing/power characterization methodologies for standard cells. Your familiarity with simulators like HSPICE and FineSim, alongside your understanding of schematic and parasitic extraction and liberty syntax requirements, makes you an ideal candidate for this role. You are well-versed in CCS statistical characterization, Verilog models, STA, and power analysis tools. Your knowledge of different EDA views for logic library such as AOCV, POCV, LVF, and EM is robust. You possess excellent scripting skills using TCL, Perl, and Python, and have a working knowledge of SNPS tools. You are a proactive team player, always ready to go the extra mile. Your strong desire to learn and explore new technologies, coupled with excellent verbal and written communication skills, sets you apart.
What Youll Be Doing:
- Developing and validating characterization flows for standard cells.
- Collaborating with cross-functional teams to ensure library validation and timing/power characterization methodologies.
- Utilizing simulators such as HSPICE and FineSim for schematic and parasitic extraction.
- Implementing CCS statistical characterization and working with Verilog models.
- Conducting STA and power analysis using relevant tools.
- Creating and maintaining scripts using TCL, Perl, and Python to streamline processes.
The Impact You Will Have:
- Enhancing the efficiency and accuracy of characterization flows and methodologies.
- Improving the validation processes for standard cell libraries, ensuring high performance and reliability.
- Facilitating seamless integration of EDA views into the design cycle.
- Contributing to the development of innovative solutions in chip design and verification.
- Supporting the adoption of new technologies and methodologies within the team.
- Driving continuous improvement and optimization of processes and tools.
What Youll Need:
- Extensive knowledge of characterization flows and library validation.
- Proficiency with simulators like HSPICE and FineSim.
- Strong understanding of schematic and parasitic extraction, and liberty syntax requirements.
- Experience with CCS statistical characterization, Verilog models, STA, and power analysis tools.
- Advanced scripting skills using TCL, Perl, and Python.
Who You Are:
- A proactive and collaborative team player.
- Excellent problem-solving and exploration skills.
- A strong desire to learn and explore new technologies.
- Exceptional verbal and written communication skills.
The Team Youll Be A Part Of:
You will be part of a dynamic and innovative team focused on driving advancements in chip design and verification. Our team is dedicated to continuous improvement and the adoption of cutting-edge technologies and methodologies. Collaboration and knowledge-sharing are at the core of our success, and we are committed to fostering a supportive and inclusive work environment.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.