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Developer Platform
To validate and debug ASIC IP cores for processors, AI models and
peripherals such as PCIe, HBM on Synopsys HAPS platform
* Prototype and bring up of the SoC from scratch on HAPS platform and
establish remote connectivity
* Knowledge of partitioning RTL code into multiple FPGAs
* Good exposure in timing closure using Vivado using HAPS toolchain
* Verilog/SV coding
* Development of validation plan
* Hardware-software co-verification
* Experience with Perl, Python, scripting (good to have)
* System Verilog and OVM/UVM (good to have)
* Experience with working on platforms such as Synopsys HAPS
* Should be able to work as a Technical lead for a team of 4 to 5
Date Posted: 17/10/2024
Job ID: 96617763
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