Ability to execute block level P&R and Timing closure activities.
Will be responsible for owning up block level P&R. Perform Netlist2GDS on blocks
Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm,16nm,14nm & below ).
Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deepsub micron processes required. Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
Expertise in Synopsys ICC2, PrimeTime physical design tools.
Skill and experience in scripting using Tcl or Perl is highly desirable
