As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Job Overview
- We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space.
- Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification.
- Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward
- Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA)
- Tabulate metrics results for analysis comparison
- Develop Place & Route recipes for optimal PPA
Minimum Qualifications
10-15 years of High Performance core Place & Route and ASIC design Implementation work experience
Preferred Qualifications
- Extensive experience in Place & Route with FC or Innovus is an absolute must
- Complete ASIC flow with low power, performance and area optimization techniques
- Experience with STA using Primetime and/or Tempus is required
- Proficient in constraint generation and validation
- Experience of multiple power domain implementation with complex UPF/CPF definition required
- Formal verification experience (Formality/Conformal)
- Perl/Tcl, Python, C++ skills are needed
- Strong problem solving and ASIC development/debugging skills
- Experience with CPU micro-architecture and their critical path
- Low power implementation techniques experience
- High speed CPU implementation
- Clock Tree Implementation Techniques for High Speed Design Implementation are required
- Exposure to Constraint management tool and Verilog coding experience
Education Requirements
Required: Bachelors, Electrical Engineering or equivalent experience
Preferred: Masters, Electrical Engineering or equivalent experience
Keywords
Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD
