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MTS SILICON DESIGN ENGINEER - Subsystem/IP Verification Lead (AECG ASIC)
The Role
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's custom silicon/ASIC designs, resulting in no bugs in the final design.
THE PERSON:You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
- Developing functional coverage & assertions.
- Own the DFT DV sign-off and ensure a bug free design
- Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models
- Work with the post-silicon team on debug support and to help root-cause any failures
- 8-10 years of Design Verification experience with strong Verilog, System Verilog, C++ and UVM/OVM knowledge
- Good understanding and exposure to SoC design and architecture
- Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects
- Ability to come with detailed testplan based on the Arch specs
- Exposure to DFT concepts such as JTAG, SCAN, MBIST, BScan, etc
- Comfortable with VCS/Verdi and excellent debug skills
- Logical in thinking and ability to gel well within a team and be a proactive member of the team.
- Good communication and leadership skills
- Continuously drive methodology improvements to improve efficiency
- Mentor junior engineers to build a high performing team
PREFERRED EXPERIENCE:- Proficient in sub-system/IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
ACADEMIC CREDENTIALS:- Bachelors or Masters degree in computer engineering/Electrical Engineering with 8-10 years of industry experience successfully delivering complex IP subsystems
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
