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Xilinx

MTS Silicon Design Engineer (Place and Route CAD Engineer )

Early Applicant
  • 17 days ago
  • Be among the first 50 applicants
Exp: 8-10 Years

Electronic Components/Semiconductors

(estd)

Job Description



WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_




MTS SILICON DESIGN ENGINEER

THE ROLE:

This position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 5nm & 3nm technology nodes as well as work closely with the EDA vendors to identify innovative solutions and track methodology issues.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems

KEY RESPONSIBILITIES:

  • Responsible for developing Place and Route methodologies for various designs at advanced technology nodes
  • Script out utilities to automate different pieces of the implementation flow
  • Support design teams at global sites through multiple PnR flow stages
  • CAD flow and Methodology development on advanced process nodes such as 7nm, 5nm are preferred

PREFERRED EXPERIENCE:

  • Hands on experience in place and route flows and tools
  • Hands on experience in industry standard PnR tools such as Fusion Compiler and ICC2
  • Hands on experience with any of synthesis, STA, or physical verification domains is a plus
  • Good control over scripting languages like Python, PERL, TCL and strong debug capabilities
  • CAD and Automation mindset

ACADEMIC CREDENTIALS:

  • Master's/Bachelor's Degree in Electronics Engineering (Minor in Computer Science preferred)
  • 8 years of experience in CAD flow and methodology development on advanced nodes such as 7nm & 5nm
  • Proficiency in one or more scripting languages namely Tcl, Perl, sed/awk
  • Work closely with design teams to support multiple areas through GDSII implementation
  • Support cross site design teams at various global sites
  • Strong problem-solving skills and analytical thinking
  • Team player, good work ethic, and excellent communication skills

#LI-SR4




Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

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Date Posted: 07/11/2024

Job ID: 99497903

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About Company

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Xilinx, Inc. was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array and creating the first fabless manufacturing model.

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Last Updated: 24-11-2024 07:16:44 PM
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