Memory Layout Engineer

Location:Bangalore

Experience:3-7 Years

Requirements

Development of key building blocks of memory architecture such as Row Decoder, IO, Control.

Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.

Compiler level integration, verification of Compiler/Custom memories.

Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.

Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.

Good problem solving and logical reasoning skills.

Good communication skills required.